From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) by mx.groups.io with SMTP id smtpd.web10.132078.1671109048876074125 for ; Thu, 15 Dec 2022 04:57:28 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=fDMBlqsO; spf=pass (domain: ventanamicro.com, ip: 209.85.215.169, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pg1-f169.google.com with SMTP id 36so4079572pgp.10 for ; Thu, 15 Dec 2022 04:57:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dJQcwIxeuj0WTtCadirZsVFU1AUp1OSGlYQ3Iu8vAY4=; b=fDMBlqsOSRSUMxz/LE3FKW5EV2QCc60QMuuVjZTRzOqxl4hCWZnHf+Z7t2wXO1W5wC Ou46ldXDnhT7HWDgot7s5P6cwTRsZCJidXiWZyY0FZbVds0CldL2519ysbUva7Ijtp/C 3+v7IFref2e0faVCbDbWRA2GlwfaeeBfF7D2ywFs+WJF0tCuH8AFSdBpxqM+rDgNf/zm za4bp4vWrihbF6b2yrxY5Hjj9r3hUXl4ZUQUg7wzVlMN4sZf3adeo8VupZpJw0NbLkwE lbi6AcQ9IVT8vW2L/+2a/Bp3DFpaE9c4vVBnf75jSSax1R2+vR/a+/+gY9KeI7ctExoW IDYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dJQcwIxeuj0WTtCadirZsVFU1AUp1OSGlYQ3Iu8vAY4=; b=Kzl+V2cJ2I1VXHiYZ3j97XEFBoBeU6Hn6ziSVIR0pw8pE9wV4dlLk6U4A6tIp8cl1i 1MzZO/FpORAXKZzhMxS5v8SRSN3awYhtxQcwe0WAIkakFHpCJsyWGAbenDKPTpyiwif0 ZYUjypc14CrVWNCIrVAdOKsJ9uQ1BkXYhCsHbhDAcc33bc7vChRUPJVzAX28W8Mc6Efc 0Hn7/os2W4FbWIdY1WcmRgme8NGKT6Db1rza+CHlS5CYjkdn16cmgNl122yh8x/y91ap 9dVZkRPShxxvgy5s/+3O3NAW/nQcIzOn0Cz+dkSi2Ts7MVuU1pBT+Nxo1xfocWq6lHcp ZRmw== X-Gm-Message-State: ANoB5plOoQ3UoRlO6iAvk3JMb3d7Mj0358gqYOUdkLEW3mtgEf+kClla w6RlraV2E37l5/T9AKu33NOV4lLJKPrqBah2OOQ= X-Google-Smtp-Source: AA0mqf4FsHah9G6G7ph8rDi9ml+wrrfpLtbk3C8hDjAqaAQPwDRQPry68f6eOBelXl51qr58TPieeA== X-Received: by 2002:a05:6a00:26c5:b0:576:dc87:a8f1 with SMTP id p5-20020a056a0026c500b00576dc87a8f1mr27059077pfw.19.1671109048018; Thu, 15 Dec 2022 04:57:28 -0800 (PST) Return-Path: Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:27 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Brijesh Singh , Erdem Aktas , James Bottomley , Min Xu , Tom Lendacky , Daniel Schaefer , Abner Chang Subject: [edk2-staging/RiscV64QemuVirt PATCH V6 20/23] OvmfPkg/Sec: Add RISC-V SEC module Date: Thu, 15 Dec 2022 18:26:23 +0530 Message-Id: <20221215125626.545372-21-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add the SEC module for RISC-V. It uses the PEI less design. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Min Xu Cc: Tom Lendacky Cc: Daniel Schaefer Cc: Abner Chang Signed-off-by: Sunil V L Acked-by: Abner Chang --- OvmfPkg/Sec/SecMainRiscV64.inf | 58 +++++++++++ OvmfPkg/Sec/RiscV64/SecMain.h | 63 ++++++++++++ OvmfPkg/Sec/RiscV64/SecMain.c | 104 ++++++++++++++++++++ OvmfPkg/Sec/RiscV64/SecEntry.S | 21 ++++ 4 files changed, 246 insertions(+) diff --git a/OvmfPkg/Sec/SecMainRiscV64.inf b/OvmfPkg/Sec/SecMainRiscV64.inf new file mode 100644 index 000000000000..79a9538aebde --- /dev/null +++ b/OvmfPkg/Sec/SecMainRiscV64.inf @@ -0,0 +1,58 @@ +## @file +# SEC Driver for RISC-V +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = SecMainRiscV64 + FILE_GUID = 16740C0A-AA84-4F62-A06D-AE328057AE07 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + ENTRY_POINT = SecMain + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = RISCV64 +# + +[Sources] + RiscV64/SecEntry.S + RiscV64/SecMain.c + RiscV64/SecMain.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + OvmfPkg/OvmfPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + PcdLib + IoLib + PeCoffLib + LzmaDecompressLib + PlatformInitLib + RiscVSbiLib + PrePiLib + +[Ppis] + gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED + gEfiTemporaryRamDonePpiGuid ## PRODUCES + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress diff --git a/OvmfPkg/Sec/RiscV64/SecMain.h b/OvmfPkg/Sec/RiscV64/SecMain.h new file mode 100644 index 000000000000..9d459dccaad4 --- /dev/null +++ b/OvmfPkg/Sec/RiscV64/SecMain.h @@ -0,0 +1,63 @@ +/** @file + Master header file for SecCore. + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SEC_MAIN_H_ +#define SEC_MAIN_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + @param SizeOfRam Size of the temporary memory available for use. + @param TempRamBase Base address of temporary ram + @param BootFirmwareVolume Base address of the Boot Firmware Volume. +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ); + +/** + Auto-generated function that calls the library constructors for all of the module's + dependent libraries. This function must be called by the SEC Core once a stack has + been established. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + VOID + ); + +#endif diff --git a/OvmfPkg/Sec/RiscV64/SecMain.c b/OvmfPkg/Sec/RiscV64/SecMain.c new file mode 100644 index 000000000000..054e49ef0c1e --- /dev/null +++ b/OvmfPkg/Sec/RiscV64/SecMain.c @@ -0,0 +1,104 @@ +/** @file + RISC-V SEC phase module for Qemu Virt. + + Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SecMain.h" + +STATIC +EFI_STATUS +EFIAPI +SecInitializePlatform ( + VOID + ) +{ + EFI_STATUS Status; + + MemoryPeimInitialization (); + + CpuPeimInitialization (); + + // Set the Boot Mode + SetBootMode (BOOT_WITH_FULL_CONFIGURATION); + + Status = PlatformPeimInitialization (); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + + @param[in] BootHartId Hardware thread ID of boot hart. + @param[in] DeviceTreeAddress Pointer to Device Tree (DTB) +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ) +{ + EFI_HOB_HANDOFF_INFO_TABLE *HobList; + EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext; + EFI_STATUS Status; + UINT64 UefiMemoryBase; + UINT64 StackBase; + + // + // Report Status Code to indicate entering SEC core + // + DEBUG (( + DEBUG_INFO, + "%a() BootHartId: 0x%x, DeviceTreeAddress=0x%x\n", + __FUNCTION__, + BootHartId, + DeviceTreeAddress + )); + + FirmwareContext.BootHartId = BootHartId; + FirmwareContext.FlattenedDeviceTree = (UINT64)DeviceTreeAddress; + SetFirmwareContextPointer (&FirmwareContext); + + StackBase = (UINT64)FixedPcdGet32 (PcdOvmfSecPeiTempRamBase); + UefiMemoryBase = StackBase + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize) - SIZE_32MB; + + // Declare the PI/UEFI memory region + HobList = HobConstructor ( + (VOID *)UefiMemoryBase, + SIZE_32MB, + (VOID *)UefiMemoryBase, + (VOID *)StackBase // The top of the UEFI Memory is reserved for the stacks + ); + PrePeiSetHobList (HobList); + + SecInitializePlatform (); + + // + // Process all libraries constructor function linked to SecMain. + // + ProcessLibraryConstructorList (); + + // Assume the FV that contains the SEC (our code) also contains a compressed FV. + Status = DecompressFirstFv (); + ASSERT_EFI_ERROR (Status); + + // Load the DXE Core and transfer control to it + Status = LoadDxeCoreFromFv (NULL, 0); + ASSERT_EFI_ERROR (Status); + // + // Should not come here. + // + UNREACHABLE (); +} diff --git a/OvmfPkg/Sec/RiscV64/SecEntry.S b/OvmfPkg/Sec/RiscV64/SecEntry.S new file mode 100644 index 000000000000..e919a3cb0e80 --- /dev/null +++ b/OvmfPkg/Sec/RiscV64/SecEntry.S @@ -0,0 +1,21 @@ +/* + Copyright (c) 2022 Ventana Micro Systems Inc. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + */ + +#include "SecMain.h" + +.text +.align 3 + +ASM_FUNC (_ModuleEntryPoint) + /* Use Temp memory as the stack for calling to C code */ + li a4, FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + li a5, FixedPcdGet32 (PcdOvmfSecPeiTempRamSize) + + /* Use Temp memory as the stack for calling to C code */ + add sp, a4, a5 + + call SecStartup -- 2.38.0