From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) by mx.groups.io with SMTP id smtpd.web11.132916.1671109003913278056 for ; Thu, 15 Dec 2022 04:56:43 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Q3Thd6Uq; spf=pass (domain: ventanamicro.com, ip: 209.85.210.172, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pf1-f172.google.com with SMTP id 65so6625072pfx.9 for ; Thu, 15 Dec 2022 04:56:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rWfFMgV//EJ97lq5RVKDrVsGis7TyZJYsnNVh55xAfY=; b=Q3Thd6UqalzVkAySBHwSqQ/NU0DksKqq69IQGamTG0dCuueGApdlju38Cnuqopq0Fx GlUXpgGRFQS/eY14pdThMS8d+BJFqPCUz/kLA9xi2h3uyAkvu6asUDddqC/lq7uWNE6H Yo7pJkemBa0L309RriZTeMSl8hydca5Ue0yx0XyTu6H7zeYUqRH5ea9QCLDbypdctspW K8hN8IO6NrnIGVXp/C62gJeFMWKsNoS1zTodAYmW2Lx1qcoqOp79C7vMP+KtJ9bqJQIN nvrSbPjhmfVhWpwOEyOyg/oCYgPXJQJ20Fl78Uln6JlZYcDNdGIkmxCDc/P9lABE2YHh ybiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rWfFMgV//EJ97lq5RVKDrVsGis7TyZJYsnNVh55xAfY=; b=Ig3ty0ZvVkUJ78d9ii0+dJVtEyaH6IpbXqxo5QxYQ0Kz23lfC+96lInA+ThxSqIQXu oZV9re3tNJeLod5eNRBB2NWSpoUKO21yyeheCzu3x77lbAmU0Wq8ij6BM5m/cgfQwjyS 0pKRQYb1twcMklXadV5EmzrGWmMVFeS5VK4Y58rGCqvm1s5vn9KowzDtvsosJWr60QgP wvZ+bdgbf9iqi2S2ytt6SxOjC+5QkkwNCwvcc4gKLpg0xEyzvFs2UDE7WG4Y5rp+AKGE D54q/PybjCaGCawAmWKuQ07wisScOoVjFeHXl0o9M1t67YlyrepSpeuzqgOuNDjnyL28 TZZQ== X-Gm-Message-State: ANoB5pltMjzZ2AL9fw6+PJduRYypU7pmVfaL7Iaf/Q7+KMJ+zYITqMhm /zBlLchmHqi5wTPUidcgwOGdb2amz1fXzk9st6k= X-Google-Smtp-Source: AA0mqf4MC2gLmSVb4RRdFzlfkEOrQlq8TFv2JoPe94nUz4+LbQM8QvYBsRi7K0uqvR7an4QHYB9SQQ== X-Received: by 2002:a62:cd0c:0:b0:577:2a9:96ef with SMTP id o12-20020a62cd0c000000b0057702a996efmr31062604pfg.28.1671109003105; Thu, 15 Dec 2022 04:56:43 -0800 (PST) Return-Path: Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.56.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:56:42 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Daniel Schaefer Subject: [edk2-staging/RiscV64QemuVirt PATCH V6 03/23] MdePkg/BaseLib: RISC-V: Add few more helper functions Date: Thu, 15 Dec 2022 18:26:06 +0530 Message-Id: <20221215125626.545372-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in BaseLib. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Daniel Schaefer Signed-off-by: Sunil V L --- MdePkg/Library/BaseLib/BaseLib.inf | 3 ++ MdePkg/Include/Library/BaseLib.h | 50 ++++++++++++++++++ MdePkg/Library/BaseLib/RiscV64/CpuScratch.S | 31 ++++++++++++ MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 23 +++++++++ MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 ++++++++++++++++++-- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 23 +++++++++ 6 files changed, 179 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 9ed46a584a14..3a48492b1a01 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -401,6 +401,9 @@ [Sources.RISCV64] RiscV64/RiscVCpuPause.S | GCC RiscV64/RiscVInterrupt.S | GCC RiscV64/FlushCache.S | GCC + RiscV64/CpuScratch.S | GCC + RiscV64/ReadTimer.S | GCC + RiscV64/RiscVMmu.S | GCC [Sources.LOONGARCH64] Math64.c diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index f3f59f21c2ea..b4f4e45a1486 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -151,6 +151,56 @@ typedef struct { #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 +VOID + RiscVSetSupervisorScratch ( + UINT64 + ); + +UINT64 +RiscVGetSupervisorScratch ( + VOID + ); + +VOID + RiscVSetSupervisorStvec ( + UINT64 + ); + +UINT64 +RiscVGetSupervisorStvec ( + VOID + ); + +UINT64 +RiscVGetSupervisorTrapCause ( + VOID + ); + +VOID + RiscVSetSupervisorAddressTranslationRegister ( + UINT64 + ); + +UINT64 +RiscVReadTimer ( + VOID + ); + +VOID +RiscVEnableTimerInterrupt ( + VOID + ); + +VOID +RiscVDisableTimerInterrupt ( + VOID + ); + +VOID +RiscVClearPendingTimerInterrupt ( + VOID + ); + #endif // defined (MDE_CPU_RISCV64) #if defined (MDE_CPU_LOONGARCH64) diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S new file mode 100644 index 000000000000..5492a500eb5e --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S @@ -0,0 +1,31 @@ +//------------------------------------------------------------------------------ +// +// CPU scratch register related functions for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------------ + +#include + +.data +.align 3 +.section .text + +// +// Set Supervisor mode scratch. +// @param a0 : Value set to Supervisor mode scratch +// +ASM_FUNC (RiscVSetSupervisorScratch) + csrw CSR_SSCRATCH, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode scratch +// +ASM_FUNC (RiscVGetSupervisorScratch) + csrr a0, CSR_SSCRATCH + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S new file mode 100644 index 000000000000..39a06efa51ef --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S @@ -0,0 +1,23 @@ +//------------------------------------------------------------------------------ +// +// Read CPU timer +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------------ + +#include + +.data +.align 3 +.section .text + +// +// Read TIME CSR. +// @retval a0 : 64-bit timer. +// +ASM_FUNC (RiscVReadTimer) + csrr a0, CSR_TIME + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S index 87b3468fc7fd..6a1b90a7e45c 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S @@ -8,13 +8,13 @@ // //------------------------------------------------------------------------------ +#include + ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts) ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt) ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts) -#define SSTATUS_SIE 0x00000002 -#define CSR_SSTATUS 0x100 - #define SSTATUS_SPP_BIT_POSITION 8 +#define SSTATUS_SPP_BIT_POSITION 8 // // This routine disables supervisor mode interrupt @@ -53,11 +53,56 @@ InTrap: ret // +// Set Supervisor mode trap vector. +// @param a0 : Value set to Supervisor mode trap vector +// +ASM_FUNC (RiscVSetSupervisorStvec) + csrrw a1, CSR_STVEC, a0 + ret + +// +// Get Supervisor mode trap vector. +// @retval a0 : Value in Supervisor mode trap vector +// +ASM_FUNC (RiscVGetSupervisorStvec) + csrr a0, CSR_STVEC + ret + +// +// Get Supervisor trap cause CSR. +// +ASM_FUNC (RiscVGetSupervisorTrapCause) + csrrs a0, CSR_SCAUSE, 0 + ret +// // This routine returns supervisor mode interrupt // status. // -ASM_PFX(RiscVGetSupervisorModeInterrupts): +ASM_FUNC (RiscVGetSupervisorModeInterrupts) csrr a0, CSR_SSTATUS andi a0, a0, SSTATUS_SIE ret +// +// This routine disables supervisor mode timer interrupt +// +ASM_FUNC (RiscVDisableTimerInterrupt) + li a0, SIP_STIP + csrc CSR_SIE, a0 + ret + +// +// This routine enables supervisor mode timer interrupt +// +ASM_FUNC (RiscVEnableTimerInterrupt) + li a0, SIP_STIP + csrs CSR_SIE, a0 + ret + +// +// This routine clears pending supervisor mode timer interrupt +// +ASM_FUNC (RiscVClearPendingTimerInterrupt) + li a0, SIP_STIP + csrc CSR_SIP, a0 + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S new file mode 100644 index 000000000000..ac8f92f38aed --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S @@ -0,0 +1,23 @@ +//------------------------------------------------------------------------------ +// +// CPU scratch register related functions for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------------ + +#include + +.data +.align 3 +.section .text + +// +// Set Supervisor Address Translation and +// Protection Register. +// +ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) + csrw CSR_SATP, a0 + ret -- 2.38.0