From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) by mx.groups.io with SMTP id smtpd.web10.132065.1671109016309471170 for ; Thu, 15 Dec 2022 04:56:56 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=oWJVGybN; spf=pass (domain: ventanamicro.com, ip: 209.85.210.172, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pf1-f172.google.com with SMTP id g1so6646986pfk.2 for ; Thu, 15 Dec 2022 04:56:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ih7sDkG06fNPhFiLpRB2hOyBYj9XLpmRpbORF4Bb5ro=; b=oWJVGybNW49QACROJ5TCEGN4k50rlIvSX4lLzl99XlZuiAcYs/fOEhw2qQdGP9353B twVuvMqvVq3rTHJO3iqvOnS7IwkmmyBlOnMCmisGAKrsgCdaliY0VQzjFEwjcU01r+0R vZOUVClMhXGe+4rGkZtBInPwG6WHI+gryvHLKW6ylVFsBD8Kb7UkmQbVBrZKUlBRlE4j eoXd8VnDT5CdC8cniSRKWgMc5jcSIk/NETrMKBR0xpTj3IyRnZuH0ugXnIr+4LMZsaoS AsI5yCUEY/RxuRgOBahqEs+f95MUWNIg4YTIUvsAnoBQTC+BzblCa85Pagem0BZjMg0W a6Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ih7sDkG06fNPhFiLpRB2hOyBYj9XLpmRpbORF4Bb5ro=; b=2c4NjIgDEpZLOrJejt5rJ48PuTqTJJXDi9SHxpjl/yYxTzpX13NrMeGM6njdK5W5N8 7ZQx6bVWUjuw0nShA1DUCGmIAroXQyyN8LgigCDxz2Eyg0K3fc9hroilsd70FnCIDoEz p8eYRcnVaFxP/3C7wwl4KFoJC8pJ+A+8kJgcDVg6MqT6N9PpxMeFUUx6o5ZhHOmSwnyW v0VyCyoAX/TWD/3o21mZbqXVKZqbzgIFTm73UNuO+jJWah/5PMrtx7zIYOWP3xDTtLJp F1ZkzXButhPpv5Nx+HkJXqm4/fURxt8B6rhGEf7W4cV5E/14+idNIfsLJowW+feVq04d At5w== X-Gm-Message-State: ANoB5pkp2EaWPqm1X5Df/IhRxmgTx/HEMAi6V+1OyitMCulfUaDaXcfX aAETQRKxLS831hy69p0ZYSWmYlbAiGACYMtvYO0= X-Google-Smtp-Source: AA0mqf7CzmQBoIW0rK6QGw/MKv6W+ZmyQWihjomeNXj+vyVQQxEDHmnadwGx0bILAt5aWxXQBgO8yQ== X-Received: by 2002:a05:6a00:2481:b0:576:3005:bb4d with SMTP id c1-20020a056a00248100b005763005bb4dmr38428752pfv.31.1671109015594; Thu, 15 Dec 2022 04:56:55 -0800 (PST) Return-Path: Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:56:55 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Abner Chang Subject: [edk2-staging/RiscV64QemuVirt PATCH V6 08/23] UefiCpuPkg/CpuTimerLib: Add RISC-V instance Date: Thu, 15 Dec 2022 18:26:11 +0530 Message-Id: <20221215125626.545372-9-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Abner Chang Signed-off-by: Sunil V L Acked-by: Abner Chang --- UefiCpuPkg/UefiCpuPkg.dsc | 1 + UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf | 32 ++++ UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c | 199 ++++++++++++++++++++ 3 files changed, 232 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 8f2be6cd1b05..2df02bf75a35 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -199,6 +199,7 @@ [Components.RISCV64] UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf UefiCpuPkg/CpuDxe/CpuDxeRiscV64.inf + UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf [BuildOptions] *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf b/UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf new file mode 100644 index 000000000000..c920e8e098b5 --- /dev/null +++ b/UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf @@ -0,0 +1,32 @@ +## @file +# RISC-V Base CPU Timer Library Instance +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = BaseRisV64CpuTimerLib + FILE_GUID = B635A600-EA24-4199-88E8-5761EEA96A51 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = TimerLib + +[Sources] + RiscV64/CpuTimerLib.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES diff --git a/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c b/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c new file mode 100644 index 000000000000..9c8efc0f3530 --- /dev/null +++ b/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c @@ -0,0 +1,199 @@ +/** @file + RISC-V instance of Timer Library. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + Stalls the CPU for at least the given number of ticks. + + Stalls the CPU for at least the given number of ticks. It's invoked by + MicroSecondDelay() and NanoSecondDelay(). + + @param Delay A period of time to delay in ticks. + +**/ +VOID +InternalRiscVTimerDelay ( + IN UINT32 Delay + ) +{ + UINT32 Ticks; + UINT32 Times; + + Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2); + Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1); + do { + // + // The target timer count is calculated here + // + Ticks = RiscVReadTimer () + Delay; + Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2); + while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) { + CpuPause (); + } + } while (Times-- > 0); +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + MicroSeconds, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ), + 1000000u + ) + ); + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + NanoSeconds, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ), + 1000000000u + ) + ); + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running performance counter. + + Retrieves the current value of a 64-bit free running performance counter. The + counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return (UINT64)RiscVReadTimer (); +} + +/**return + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter starts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end with + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartValue + is less than EndValue, then the performance counter counts up. If StartValue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a StartValue + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with before + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue != NULL) { + *StartValue = 0; + } + + if (EndValue != NULL) { + *EndValue = 32 - 1; + } + + return PcdGet64 (PcdCpuCoreCrystalClockFrequency); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance counter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 NanoSeconds; + UINT32 Remainder; + + // + // Ticks + // Time = --------- x 1,000,000,000 + // Frequency + // + NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdCpuCoreCrystalClockFrequency), &Remainder), 1000000000u); + + // + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000) + // will not overflow 64-bit. + // + NanoSeconds += DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u), PcdGet64 (PcdCpuCoreCrystalClockFrequency)); + + return NanoSeconds; +} -- 2.38.0