From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.46058.1671525777169185136 for ; Tue, 20 Dec 2022 00:43:05 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=J2URXqw3; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671525785; x=1703061785; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f9Ipd6Rj2p2t+Xo9uGiCLDC6v3rBSJ9ACmPr2/uOAQ8=; b=J2URXqw3O8GC/rRDS/+xDPlbVA87H58rU4q3UHx8dmChSEIbFehjRyED i5tAgKdF/j6y9iOpar+1juZCpFuNrJiCoX3+JfMprrD8J4xNE4q1UAJ7+ J+0clYore+v1YXXgI8EeMZ1x4SsAp5EpTUYulRRM54JxeSnAv+/ax7mri 3sMEEcCbiStXkPXbcXbOV0/OhoFwqN7HXwea1CIJ+tA+FksTo2EDiZMXY 4vq1iLGXsbf9eic0m4P8SCEbeUK8+2mfgl3bKBADqk4U50UdBFUj5/cjz RMGDL5Whxzl3Laze1PxcK/zw+/29HpS7WXV4W/yRdP/jWU+/EXKP2xUqs A==; X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="383908291" X-IronPort-AV: E=Sophos;i="5.96,258,1665471600"; d="scan'208";a="383908291" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2022 00:43:05 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="628644656" X-IronPort-AV: E=Sophos;i="5.96,259,1665471600"; d="scan'208";a="628644656" Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.29.12]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2022 00:43:02 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min M Xu , Erdem Aktas , Gerd Hoffmann , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [PATCH V2 4/6] OvmfPkg/Sec: Move TDX APs related nasm code to IntelTdxAPs.nasm Date: Tue, 20 Dec 2022 16:42:38 +0800 Message-Id: <20221220084240.1922-5-min.m.xu@intel.com> X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: <20221220084240.1922-1-min.m.xu@intel.com> References: <20221220084240.1922-1-min.m.xu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Min M Xu BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4172 This patch moves the TDX APs nasm code from SecEntry.nasm to IntelTdxAPs.nasm. IntelTdxX64 and OvmfPkgX64 use the same nasm so that it can be easier to be managed. In the following patch there will be AcceptMemory related changes in IntelTdxAPs.nasm. Cc: Erdem Aktas Cc: Gerd Hoffmann Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/IntelTdx/Sec/X64/IntelTdxAPs.nasm | 58 +++++++++++++++++++++++ OvmfPkg/IntelTdx/Sec/X64/SecEntry.nasm | 58 ++--------------------- OvmfPkg/Sec/X64/SecEntry.nasm | 58 ++--------------------- 3 files changed, 68 insertions(+), 106 deletions(-) create mode 100644 OvmfPkg/IntelTdx/Sec/X64/IntelTdxAPs.nasm diff --git a/OvmfPkg/IntelTdx/Sec/X64/IntelTdxAPs.nasm b/OvmfPkg/IntelTdx/Sec/X64/IntelTdxAPs.nasm new file mode 100644 index 000000000000..034ac0ee9421 --- /dev/null +++ b/OvmfPkg/IntelTdx/Sec/X64/IntelTdxAPs.nasm @@ -0,0 +1,58 @@ +;------------------------------------------------------------------------------ +; @file +; Intel TDX APs +; +; Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;------------------------------------------------------------------------------ + +%include "TdxCommondefs.inc" + + ; + ; Note: BSP never gets here. APs will be unblocked by DXE + ; + ; R8 [31:0] NUM_VCPUS + ; [63:32] MAX_VCPUS + ; R9 [31:0] VCPU_INDEX + ; +ParkAp: + +do_wait_loop: + ; + ; register itself in [rsp + CpuArrivalOffset] + ; + mov rax, 1 + lock xadd dword [rsp + CpuArrivalOffset], eax + inc eax + +.check_arrival_cnt: + cmp eax, r8d + je .check_command + mov eax, dword[rsp + CpuArrivalOffset] + jmp .check_arrival_cnt + +.check_command: + mov eax, dword[rsp + CommandOffset] + cmp eax, MpProtectedModeWakeupCommandNoop + je .check_command + + cmp eax, MpProtectedModeWakeupCommandWakeup + je .do_wakeup + + ; Don't support this command, so ignore + jmp .check_command + +.do_wakeup: + ; + ; BSP sets these variables before unblocking APs + ; RAX: WakeupVectorOffset + ; RBX: Relocated mailbox address + ; RBP: vCpuId + ; + mov rax, 0 + mov eax, dword[rsp + WakeupVectorOffset] + mov rbx, [rsp + WakeupArgsRelocatedMailBox] + nop + jmp rax + jmp $ diff --git a/OvmfPkg/IntelTdx/Sec/X64/SecEntry.nasm b/OvmfPkg/IntelTdx/Sec/X64/SecEntry.nasm index 4528fec309a0..5a38c4213916 100644 --- a/OvmfPkg/IntelTdx/Sec/X64/SecEntry.nasm +++ b/OvmfPkg/IntelTdx/Sec/X64/SecEntry.nasm @@ -10,7 +10,6 @@ ;------------------------------------------------------------------------------ #include -%include "TdxCommondefs.inc" DEFAULT REL SECTION .text @@ -49,6 +48,7 @@ ASM_PFX(_ModuleEntryPoint): cmp byte[eax], VM_GUEST_TYPE_TDX jne InitStack + %define TDCALL_TDINFO 1 mov rax, TDCALL_TDINFO tdcall @@ -62,7 +62,9 @@ ASM_PFX(_ModuleEntryPoint): mov rax, r9 and rax, 0xffff test rax, rax - jne ParkAp + jz InitStack + mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) + jmp ParkAp InitStack: @@ -98,54 +100,4 @@ InitStack: sub rsp, 0x20 call ASM_PFX(SecCoreStartupWithStack) - ; - ; Note: BSP never gets here. APs will be unblocked by DXE - ; - ; R8 [31:0] NUM_VCPUS - ; [63:32] MAX_VCPUS - ; R9 [31:0] VCPU_INDEX - ; -ParkAp: - - mov rbp, r9 - -.do_wait_loop: - mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) - - ; - ; register itself in [rsp + CpuArrivalOffset] - ; - mov rax, 1 - lock xadd dword [rsp + CpuArrivalOffset], eax - inc eax - -.check_arrival_cnt: - cmp eax, r8d - je .check_command - mov eax, dword[rsp + CpuArrivalOffset] - jmp .check_arrival_cnt - -.check_command: - mov eax, dword[rsp + CommandOffset] - cmp eax, MpProtectedModeWakeupCommandNoop - je .check_command - - cmp eax, MpProtectedModeWakeupCommandWakeup - je .do_wakeup - - ; Don't support this command, so ignore - jmp .check_command - -.do_wakeup: - ; - ; BSP sets these variables before unblocking APs - ; RAX: WakeupVectorOffset - ; RBX: Relocated mailbox address - ; RBP: vCpuId - ; - mov rax, 0 - mov eax, dword[rsp + WakeupVectorOffset] - mov rbx, [rsp + WakeupArgsRelocatedMailBox] - nop - jmp rax - jmp $ +%include "IntelTdxAPs.nasm" diff --git a/OvmfPkg/Sec/X64/SecEntry.nasm b/OvmfPkg/Sec/X64/SecEntry.nasm index 4528fec309a0..0f82051720da 100644 --- a/OvmfPkg/Sec/X64/SecEntry.nasm +++ b/OvmfPkg/Sec/X64/SecEntry.nasm @@ -10,7 +10,6 @@ ;------------------------------------------------------------------------------ #include -%include "TdxCommondefs.inc" DEFAULT REL SECTION .text @@ -49,6 +48,7 @@ ASM_PFX(_ModuleEntryPoint): cmp byte[eax], VM_GUEST_TYPE_TDX jne InitStack + %define TDCALL_TDINFO 1 mov rax, TDCALL_TDINFO tdcall @@ -62,7 +62,9 @@ ASM_PFX(_ModuleEntryPoint): mov rax, r9 and rax, 0xffff test rax, rax - jne ParkAp + jz InitStack + mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) + jmp ParkAp InitStack: @@ -98,54 +100,4 @@ InitStack: sub rsp, 0x20 call ASM_PFX(SecCoreStartupWithStack) - ; - ; Note: BSP never gets here. APs will be unblocked by DXE - ; - ; R8 [31:0] NUM_VCPUS - ; [63:32] MAX_VCPUS - ; R9 [31:0] VCPU_INDEX - ; -ParkAp: - - mov rbp, r9 - -.do_wait_loop: - mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) - - ; - ; register itself in [rsp + CpuArrivalOffset] - ; - mov rax, 1 - lock xadd dword [rsp + CpuArrivalOffset], eax - inc eax - -.check_arrival_cnt: - cmp eax, r8d - je .check_command - mov eax, dword[rsp + CpuArrivalOffset] - jmp .check_arrival_cnt - -.check_command: - mov eax, dword[rsp + CommandOffset] - cmp eax, MpProtectedModeWakeupCommandNoop - je .check_command - - cmp eax, MpProtectedModeWakeupCommandWakeup - je .do_wakeup - - ; Don't support this command, so ignore - jmp .check_command - -.do_wakeup: - ; - ; BSP sets these variables before unblocking APs - ; RAX: WakeupVectorOffset - ; RBX: Relocated mailbox address - ; RBP: vCpuId - ; - mov rax, 0 - mov eax, dword[rsp + WakeupVectorOffset] - mov rbx, [rsp + WakeupArgsRelocatedMailBox] - nop - jmp rax - jmp $ +%include "../../IntelTdx/Sec/X64/IntelTdxAPs.nasm" -- 2.29.2.windows.2