From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web11.129091.1672018441335739938 for ; Sun, 25 Dec 2022 17:34:01 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=EfamgqAD; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672018441; x=1703554441; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RNQyPrlbVNPapfnvZDuzYg4vl3S8uHdIrM9OqIz52H4=; b=EfamgqADRqGoBYI+4t+tXR1seF7v3oUw+HhRJ6OOnbSI59WVWsYAc+FS KpUYIuE6RyiM/okI1XS90RsUYRDWWmozpce2jvJjzUVlmiozeWW6MqTiG glIIjkKMEfA6XviVLXG2f3VBe0E310eSGpPTNaU6XrbaaZOPwcARgXhwh Ulrsd6qfzfZqzDuHhKJhiknBFSFQVLP3WwxSy0cK0oUXV872g1NURALi8 fn4+nSPyLGL+FfRoovTyQF4oRW62ucru8TKRTBKu+/bh9bpOPi5nca/XH cgmYXV4R+tcA6sdzwXFqmRREEMxRz//TOLUjjgGScyITNIca5OEgvXaWA A==; X-IronPort-AV: E=McAfee;i="6500,9779,10571"; a="347697082" X-IronPort-AV: E=Sophos;i="5.96,274,1665471600"; d="scan'208";a="347697082" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Dec 2022 17:34:00 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10571"; a="826755467" X-IronPort-AV: E=Sophos;i="5.96,274,1665471600"; d="scan'208";a="826755467" Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.169.98]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Dec 2022 17:33:56 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min M Xu , Erdem Aktas , Gerd Hoffmann , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [PATCH V1 3/3] OvmfPkg/PlatformPei: Adjust LowerMemorySize in PublishPeiMemory Date: Mon, 26 Dec 2022 09:33:38 +0800 Message-Id: <20221226013338.1924-4-min.m.xu@intel.com> X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: <20221226013338.1924-1-min.m.xu@intel.com> References: <20221226013338.1924-1-min.m.xu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Min M Xu BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4181 With the introduce of PcdAcceptMemoryEndAddress, TDVF may accept less memory than LowerMemorySizse. So it should be adjusted in PublishPeiMemory(). Cc: Erdem Aktas Cc: Gerd Hoffmann Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/PlatformPei/MemDetect.c | 13 +++++++++++++ OvmfPkg/PlatformPei/PlatformPei.inf | 1 + 2 files changed, 14 insertions(+) diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index 3d8375320dcb..12a1ad46f1ca 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -270,8 +270,21 @@ PublishPeiMemory ( UINT32 PeiMemoryCap; UINT32 S3AcpiReservedMemoryBase; UINT32 S3AcpiReservedMemorySize; + UINT64 AcceptMemoryEndAddress; LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + + // + // In Tdx guest there may be less memory accepted than LowerMemorySize. + // So LowerMemorySize need to be adjusted accordingly. + // + if (TdIsEnabled ()) { + AcceptMemoryEndAddress = FixedPcdGet64 (PcdAcceptMemoryEndAddress); + if ((AcceptMemoryEndAddress < SIZE_4GB) && (LowerMemorySize > (UINT32)(UINTN)AcceptMemoryEndAddress)) { + LowerMemorySize = (UINT32)(UINTN)AcceptMemoryEndAddress; + } + } + if (PlatformInfoHob->SmmSmramRequire) { // // TSEG is chipped from the end of low RAM diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf index 1fadadeb5565..c87d2fa25c08 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -130,6 +130,7 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsSize + gUefiOvmfPkgTokenSpaceGuid.PcdAcceptMemoryEndAddress [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdCsmEnable -- 2.29.2.windows.2