From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) by mx.groups.io with SMTP id smtpd.web10.148441.1672103817487386324 for ; Mon, 26 Dec 2022 17:16:57 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf.com header.s=google header.b=bY2BFHV5; spf=pass (domain: semihalf.com, ip: 209.85.167.45, mailfrom: mw@semihalf.com) Received: by mail-lf1-f45.google.com with SMTP id b3so17822678lfv.2 for ; Mon, 26 Dec 2022 17:16:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=LIWjvl3ib76joCGoDADTr8amkfcApXNMljuRfpL8RXg=; b=bY2BFHV5Cn9QGpvoTfrDgo3e5BLxbvNsSiUOxfywe5+tgAYK8CG4TG4osF5TBYG1cr P9qZPKnHUaqPjTR6AY6NB3NTXSW3pzKT5YhDkaSqdACnOF2VZFbrf22bQKhlJ2IbCYxA s1NGOLN9zQ9ORqiIVgPYmx2wmNqW0QyMU/7c4yKDSyusnyRhfjOpjwqKsfAa1wyjGN0S wA4eoAdhhpNrn1KH6G5sTXa2U4iak097F3dJyG/Xk7tj9rxhGVdizg0rXHdO/QSWrwdF tjSLYcijrDqBEouKbLy+DKlWVUDxDOz5XdIURHdMMmk52MiqJBG2+i2x5Rn8K5dVBEVD dzCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=LIWjvl3ib76joCGoDADTr8amkfcApXNMljuRfpL8RXg=; b=KaRbLLAngNFAe2FzMFLUEMcm+/TVjoi/apGTuVaG3cWhA/USpWPO95NN6pJ0k8KyAS YS2BzrQaA1bX/b6wMIgTunzRyvTu61iYhUTw2f+7t9McGg2nPYR9SCOs3gtxnlQVqNVy GTa+xfoQp6H7vHPlMaNT9/yQyk/1JY4vGAig+EgFbcUkEtCbWynmlY8tBsx+eLbH0YF6 wr0kEwMtukUzDBQmOY8qWXEpV3P36Bc/Vp6IXoTLIgdE9pAEgMAe39Ac+QQofcZBG/8n dgtkSZFOfxq9QYlHV4ThispWrNreOFCbFrAqZxQdHJMvEBMcxSVitgf7Lu2bkB5esOL3 Sx9A== X-Gm-Message-State: AFqh2koM9guuNRCecDd6wvkmaad3yZ90B+DJ9eNX+gAt2eNAfQZF5FiE 3JQscfGeQYwzf7vaWAGdx8UEBr+PFKkg4P8W X-Google-Smtp-Source: AMrXdXsOdMuRMyEH/DOV73KCo+1G2BzObgXyzB1Gf9DkPU8c+SSxh3mVP6AJLFTeQgiACrz114/0Lw== X-Received: by 2002:ac2:551d:0:b0:4ca:fe5f:bc0e with SMTP id j29-20020ac2551d000000b004cafe5fbc0emr4404272lfk.21.1672103815696; Mon, 26 Dec 2022 17:16:55 -0800 (PST) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id y2-20020ac24202000000b004bd8534ebbcsm2004921lfh.37.2022.12.26.17.16.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Dec 2022 17:16:55 -0800 (PST) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, ardb+tianocore@kernel.org, mw@semihalf.com, jaz@semihalf.com Subject: [edk2-non-osi: PATCH] SolidRun/Cn913xCEx7Eval: Add missing switch CPU port mode description Date: Tue, 27 Dec 2022 02:15:21 +0100 Message-Id: <20221227011521.812930-1-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The DSA device tree binding requires setting the CPU port mode explicitly and it was missing in the CN913x CEx7 Evaluation Board swtich description. Fix that. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts index 50e6d69..d42911c 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts @@ -285,6 +285,11 @@ reg =3D <5>;=0D label =3D "cpu";=0D ethernet =3D <&cp0_eth2>;=0D + phy-mode =3D "2500base-x";=0D + fixed-link {=0D + speed =3D <2500>;=0D + full-duplex;=0D + };=0D };=0D };=0D =0D --=20 2.29.0