From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.57912.1672725411544685909 for ; Mon, 02 Jan 2023 21:56:51 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=ZGv+PJvG; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672725411; x=1704261411; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=lUiU+vErpt94KM/58wTyuDDp7vf6Z/ZvvCooxQQo/K0=; b=ZGv+PJvGIqEqDtiClbvBagfTJUaHDCYhTeVjjMICRrQ3TZzDBBlCjhol y7+IweAF0pGQk6t7AuHGyHhM5z2gqZbG1Y8XTzJaJzsk/K2OyHUWv/oWj 3T158g8UzWuYkDZDrIytUwTLINitpicR030Y+llgoqMiUIOFSzHdSSvhh wnTOGXf8rG0BaM6wQxw2y+jkaxvkpo78E3T7myykCSx5+U3GzuLiqtMa6 rd50k98ogHrjATvFZBi6kEleOmA6jSyA72a8IZJLwLgCIrTxyDVExVH3n ktaqBSI6SiFrArAVhgupmrhdoN9w9/pDJ8XsJHZrSOSFr4m4LMml0dt9T g==; X-IronPort-AV: E=McAfee;i="6500,9779,10578"; a="319295622" X-IronPort-AV: E=Sophos;i="5.96,296,1665471600"; d="scan'208";a="319295622" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2023 21:56:51 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10578"; a="648097054" X-IronPort-AV: E=Sophos;i="5.96,296,1665471600"; d="scan'208";a="648097054" Received: from duntan-mobl.ccr.corp.intel.com ([10.239.157.24]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2023 21:56:49 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar Subject: [Patch V4] UefiCpuPkg/PiSmmCpuDxeSmm:Fix PF issue caused by smm page table code Date: Tue, 3 Jan 2023 13:56:17 +0800 Message-Id: <20230103055617.2103-1-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When setting new page table pool to RO, only disable/enable WP when Cr0.WP has been set to 1 to fix potential PF caused by b822be1a20 (UefiCpuPkg/PiSmmCpuDxeSmm: Introduce page table pool mechanism). With previous code, if someone want to modify the page table and Cr0.WP has been cleared before modify page table, Cr0.WP may be set to 1 again since new pool may be generated during this process Then PF fault may happens. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 40 ++++++++++++++++++++++++++++------------ 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 4bb23f6920..bab7f1887b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -67,8 +67,10 @@ InitializePageTablePool ( IN UINTN PoolPages ) { - VOID *Buffer; - BOOLEAN CetEnabled; + VOID *Buffer; + BOOLEAN CetEnabled; + BOOLEAN WpEnabled; + IA32_CR0 Cr0; // // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for @@ -106,21 +108,35 @@ InitializePageTablePool ( // if (mIsReadOnlyPageTable) { CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE; - if (CetEnabled) { + Cr0.UintN = AsmReadCr0 (); + WpEnabled = (Cr0.Bits.WP != 0) ? TRUE : FALSE; + if (WpEnabled) { + if (CetEnabled) { + // + // CET must be disabled if WP is disabled. Disable CET before clearing CR0.WP. + // + DisableCet (); + } + // - // CET must be disabled if WP is disabled. + // Only disable/enable WP when Cr0.Bits.WP has been set to 1. // - DisableCet (); + Cr0.Bits.WP = 0; + AsmWriteCr0 (Cr0.UintN); } - AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP); SmmSetMemoryAttributes ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer, EFI_PAGES_TO_SIZE (PoolPages), EFI_MEMORY_RO); - AsmWriteCr0 (AsmReadCr0 () | CR0_WP); - if (CetEnabled) { - // - // re-enable CET. - // - EnableCet (); + if (WpEnabled) { + Cr0.UintN = AsmReadCr0 (); + Cr0.Bits.WP = 1; + AsmWriteCr0 (Cr0.UintN); + + if (CetEnabled) { + // + // re-enable CET. + // + EnableCet (); + } } } -- 2.31.1.windows.1