From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.5512.1672810932996305792 for ; Tue, 03 Jan 2023 21:42:13 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=AlqCXyWf; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: zhiguang.liu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672810933; x=1704346933; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=thBSQuvAKdDXgeI/6UHgrpAvcc61uH6gXMMNxufX2LU=; b=AlqCXyWfu/PPncIOEy9ztnATlfDJoJL4Ik/YD5fbjUpA+fg5lmsnL1O1 a8QHxuG9G3nCxacuX4/CPM8IYQ2o/GsxyVGkEY118wB/bEO1UoaqUhnbX jPTc8Su79d2EPWqcAAr/+iDsqKuZUiAYOF/IIHYbmGL/u22WSBJ+uBn7/ gVUShxRXxU4E0hpjOXP5PhQWIT6uHJZaBj1lC/QaXF7k6NAc/ix00zPZ1 zCyEIsCMRXptnGOIeBC9srI+KIscjno5TiMVdAHWhMvGzV5tjSogjcbjY 4r0zoqhw1chNpRH+eGM3VZMvVrbHZAqed2G3SBPmU+eeb5pac/crJugoy A==; X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="302214816" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="302214816" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 21:42:12 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="723523717" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="723523717" Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 21:42:10 -0800 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Ray Ni , Rahul Kumar , Eric Dong Subject: [PATCH] UefiCpuPkg: Fix SMM code hangs when InitPaging Date: Wed, 4 Jan 2023 13:41:18 +0800 Message-Id: <20230104054118.280-1-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4246 In function InitPaging, NumberOfPml5Entries is calculated by below code NumberOfPml5Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 48); If the SizeOfMemorySpace is larger than 48, NumberOfPml5Entries will be larger than 1. However, this doesn't make sense if the hardware doesn't support 5 level page table. Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Eric Dong Signed-off-by: Zhiguang Liu --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c index c1efda7126..c597b39b8c 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -1,7 +1,7 @@ /** @file Enable SMM profile. -Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2012 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -587,15 +587,17 @@ InitPaging ( } SizeOfMemorySpace = HighBitSet64 (gPhyMask) + 1; + ASSERT (SizeOfMemorySpace <= 52); + // - // Calculate the table entries of PML4E and PDPTE. + // Calculate the table entries of PML5E, PML4E and PDPTE. // NumberOfPml5Entries = 1; - if (SizeOfMemorySpace > 48) { + if (Enable5LevelPaging && (SizeOfMemorySpace > 48)) { NumberOfPml5Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 48); - SizeOfMemorySpace = 48; } + SizeOfMemorySpace = SizeOfMemorySpace > 48 ? 48 : SizeOfMemorySpace; NumberOfPml4Entries = 1; if (SizeOfMemorySpace > 39) { NumberOfPml4Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 39); -- 2.31.1.windows.1