From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.groups.io with SMTP id smtpd.web10.98860.1673338891370149389 for ; Tue, 10 Jan 2023 00:21:31 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=YZA95C1g; spf=pass (domain: redhat.com, ip: 170.10.129.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673338890; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bSRYBMARYjpoaDRWYoJKk449FdY4KXLUR0opOv6qnhg=; b=YZA95C1gxQu7g908ud1YR7xdZ4MGZJzjwhaoig+clXdazbaOtYMWDf11B6V+neu/jvuY68 Y0dq/GQygSLAc25aPCtXkCUZkGGbvji6uO0yvw5L2zPsyrKYc1Q0ldjfa1t0w3w58CvS33 cfv5dZhva2oJGv432Sk3TjlQCxiybek= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-635-CvCWsQY_PyGo0cLD32j23w-1; Tue, 10 Jan 2023 03:21:27 -0500 X-MC-Unique: CvCWsQY_PyGo0cLD32j23w-1 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 2837985CCE2; Tue, 10 Jan 2023 08:21:27 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.238]) by smtp.corp.redhat.com (Postfix) with ESMTPS id AEBE9492C14; Tue, 10 Jan 2023 08:21:26 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id E45181800619; Tue, 10 Jan 2023 09:21:23 +0100 (CET) From: "Gerd Hoffmann" To: devel@edk2.groups.io Cc: Pawel Polawski , Jiewen Yao , Oliver Steffen , Jordan Justen , =?UTF-8?q?L=C3=A1szl=C3=B3=20=C3=89rsek?= , Ard Biesheuvel , Gerd Hoffmann Subject: [PATCH v2 2/4] OvmfPkg/PlatformInitLib: Add PlatformGetLowMemoryCB Date: Tue, 10 Jan 2023 09:21:21 +0100 Message-Id: <20230110082123.159521-3-kraxel@redhat.com> In-Reply-To: <20230110082123.159521-1-kraxel@redhat.com> References: <20230110082123.159521-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true Add PlatformGetLowMemoryCB() callback function for use with PlatformScanE820(). It stores the low memory size in PlatformInfoHob->LowMemory. This replaces calls to PlatformScanOrAdd64BitE820Ram() with non-NULL LowMemory. Also change PlatformGetSystemMemorySizeBelow4gb() to likewise set PlatformInfoHob->LowMemory instead of returning the value. Update all Callers to the new convention. Signed-off-by: Gerd Hoffmann --- OvmfPkg/Include/Library/PlatformInitLib.h | 3 +- OvmfPkg/Library/PeilessStartupLib/Hob.c | 3 +- .../PeilessStartupLib/PeilessStartup.c | 7 +- OvmfPkg/Library/PlatformInitLib/MemDetect.c | 69 +++++++++++++------ OvmfPkg/Library/PlatformInitLib/Platform.c | 7 +- OvmfPkg/PlatformPei/MemDetect.c | 3 +- 6 files changed, 59 insertions(+), 33 deletions(-) diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Library/PlatformInitLib.h index bf6f90a5761c..051b31191194 100644 --- a/OvmfPkg/Include/Library/PlatformInitLib.h +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -26,6 +26,7 @@ typedef struct { BOOLEAN Q35SmramAtDefaultSmbase; UINT16 Q35TsegMbytes; + UINT32 LowMemory; UINT64 FirstNonAddress; UINT8 PhysMemAddressWidth; UINT32 Uc32Base; @@ -144,7 +145,7 @@ PlatformQemuUc32BaseInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ); -UINT32 +VOID EFIAPI PlatformGetSystemMemorySizeBelow4gb ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob diff --git a/OvmfPkg/Library/PeilessStartupLib/Hob.c b/OvmfPkg/Library/PeilessStartupLib/Hob.c index 630ce445ebec..784a8ba194de 100644 --- a/OvmfPkg/Library/PeilessStartupLib/Hob.c +++ b/OvmfPkg/Library/PeilessStartupLib/Hob.c @@ -41,8 +41,9 @@ ConstructSecHobList ( EFI_HOB_PLATFORM_INFO PlatformInfoHob; ZeroMem (&PlatformInfoHob, sizeof (PlatformInfoHob)); + PlatformGetSystemMemorySizeBelow4gb (&PlatformInfoHob); PlatformInfoHob.HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID); - LowMemorySize = PlatformGetSystemMemorySizeBelow4gb (&PlatformInfoHob); + LowMemorySize = PlatformInfoHob.LowMemory; ASSERT (LowMemorySize != 0); LowMemoryStart = FixedPcdGet32 (PcdOvmfDxeMemFvBase) + FixedPcdGet32 (PcdOvmfDxeMemFvSize); LowMemorySize -= LowMemoryStart; diff --git a/OvmfPkg/Library/PeilessStartupLib/PeilessStartup.c b/OvmfPkg/Library/PeilessStartupLib/PeilessStartup.c index 380e71597206..928120d183ba 100644 --- a/OvmfPkg/Library/PeilessStartupLib/PeilessStartup.c +++ b/OvmfPkg/Library/PeilessStartupLib/PeilessStartup.c @@ -41,8 +41,7 @@ InitializePlatform ( EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - UINT32 LowerMemorySize; - VOID *VariableStore; + VOID *VariableStore; DEBUG ((DEBUG_INFO, "InitializePlatform in Pei-less boot\n")); PlatformDebugDumpCmos (); @@ -70,14 +69,14 @@ InitializePlatform ( PlatformInfoHob->PcdCpuBootLogicalProcessorNumber )); - LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); PlatformQemuUc32BaseInitialization (PlatformInfoHob); DEBUG (( DEBUG_INFO, "Uc32Base = 0x%x, Uc32Size = 0x%x, LowerMemorySize = 0x%x\n", PlatformInfoHob->Uc32Base, PlatformInfoHob->Uc32Size, - LowerMemorySize + PlatformInfoHob->LowMemory )); VariableStore = PlatformReserveEmuVariableNvStore (); diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/PlatformInitLib/MemDetect.c index a2a4dc043f2e..63329c4e796a 100644 --- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c @@ -51,18 +51,16 @@ PlatformQemuUc32BaseInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - UINT32 LowerMemorySize; - if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) { return; } if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { - LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32); - ASSERT (PcdGet64 (PcdPciExpressBaseAddress) >= LowerMemorySize); + ASSERT (PcdGet64 (PcdPciExpressBaseAddress) >= PlatformInfoHob->LowMemory); - if (LowerMemorySize <= BASE_2GB) { + if (PlatformInfoHob->LowMemory <= BASE_2GB) { // Newer qemu with gigabyte aligned memory, // 32-bit pci mmio window is 2G -> 4G then. PlatformInfoHob->Uc32Base = BASE_2GB; @@ -92,8 +90,8 @@ PlatformQemuUc32BaseInitialization ( // variable MTRR suffices by truncating the size to a whole power of two, // while keeping the end affixed to 4GB. This will round the base up. // - LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); - PlatformInfoHob->Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize)); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + PlatformInfoHob->Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - PlatformInfoHob->LowMemory)); PlatformInfoHob->Uc32Base = (UINT32)(SIZE_4GB - PlatformInfoHob->Uc32Size); // // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB. @@ -101,13 +99,13 @@ PlatformQemuUc32BaseInitialization ( // ASSERT (PlatformInfoHob->Uc32Base >= BASE_2GB); - if (PlatformInfoHob->Uc32Base != LowerMemorySize) { + if (PlatformInfoHob->Uc32Base != PlatformInfoHob->LowMemory) { DEBUG (( DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for " "an UC32 size of 0x%x\n", __FUNCTION__, - LowerMemorySize, + PlatformInfoHob->LowMemory, PlatformInfoHob->Uc32Base, PlatformInfoHob->Uc32Size )); @@ -279,6 +277,33 @@ PlatformGetFirstNonAddressCB ( } } +/** + Store the low (below 4G) memory size in + PlatformInfoHob->LowMemory +**/ +VOID +PlatformGetLowMemoryCB ( + IN EFI_E820_ENTRY64 *E820Entry, + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + UINT64 Candidate; + + if (E820Entry->Type != EfiAcpiAddressRangeMemory) { + return; + } + + Candidate = E820Entry->BaseAddr + E820Entry->Length; + if (Candidate >= BASE_4GB) { + return; + } + + if (PlatformInfoHob->LowMemory < Candidate) { + DEBUG ((DEBUG_INFO, "%a: LowMemory=0x%Lx\n", __FUNCTION__, Candidate)); + PlatformInfoHob->LowMemory = Candidate; + } +} + /** Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map, call the passed callback for each entry. @@ -395,14 +420,13 @@ GetHighestSystemMemoryAddressFromPvhMemmap ( return HighestAddress; } -UINT32 +VOID EFIAPI PlatformGetSystemMemorySizeBelow4gb ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { EFI_STATUS Status; - UINT64 LowerMemorySize = 0; UINT8 Cmos0x34; UINT8 Cmos0x35; @@ -410,12 +434,13 @@ PlatformGetSystemMemorySizeBelow4gb ( (CcProbe () != CcGuestTypeIntelTdx)) { // Get the information from PVH memmap - return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE); + PlatformInfoHob->LowMemory = GetHighestSystemMemoryAddressFromPvhMemmap (TRUE); + return; } - Status = PlatformScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); - if ((Status == EFI_SUCCESS) && (LowerMemorySize > 0)) { - return (UINT32)LowerMemorySize; + Status = PlatformScanE820 (PlatformGetLowMemoryCB, PlatformInfoHob); + if ((Status == EFI_SUCCESS) && (PlatformInfoHob->LowMemory > 0)) { + return; } // @@ -430,7 +455,7 @@ PlatformGetSystemMemorySizeBelow4gb ( Cmos0x34 = (UINT8)PlatformCmosRead8 (0x34); Cmos0x35 = (UINT8)PlatformCmosRead8 (0x35); - return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB); + PlatformInfoHob->LowMemory = ((((UINTN)Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB; } STATIC @@ -965,7 +990,6 @@ PlatformQemuInitializeRam ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - UINT64 LowerMemorySize; UINT64 UpperMemorySize; MTRR_SETTINGS MtrrSettings; EFI_STATUS Status; @@ -975,7 +999,7 @@ PlatformQemuInitializeRam ( // // Determine total memory size available // - LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); if (PlatformInfoHob->BootMode == BOOT_ON_S3_RESUME) { // @@ -1009,14 +1033,14 @@ PlatformQemuInitializeRam ( UINT32 TsegSize; TsegSize = PlatformInfoHob->Q35TsegMbytes * SIZE_1MB; - PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); + PlatformAddMemoryRangeHob (BASE_1MB, PlatformInfoHob->LowMemory - TsegSize); PlatformAddReservedMemoryBaseSizeHob ( - LowerMemorySize - TsegSize, + PlatformInfoHob->LowMemory - TsegSize, TsegSize, TRUE ); } else { - PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize); + PlatformAddMemoryRangeHob (BASE_1MB, PlatformInfoHob->LowMemory); } // @@ -1194,9 +1218,10 @@ PlatformQemuInitializeRamForS3 ( // Make sure the TSEG area that we reported as a reserved memory resource // cannot be used for reserved memory allocations. // + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); TsegSize = PlatformInfoHob->Q35TsegMbytes * SIZE_1MB; BuildMemoryAllocationHob ( - PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize, + PlatformInfoHob->LowMemory - TsegSize, TsegSize, EfiReservedMemoryType ); diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/PlatformInitLib/Platform.c index 3e13c5d4b34f..9ab0342fd8c0 100644 --- a/OvmfPkg/Library/PlatformInitLib/Platform.c +++ b/OvmfPkg/Library/PlatformInitLib/Platform.c @@ -128,7 +128,6 @@ PlatformMemMapInitialization ( { UINT64 PciIoBase; UINT64 PciIoSize; - UINT32 TopOfLowRam; UINT64 PciExBarBase; UINT32 PciBase; UINT32 PciSize; @@ -150,7 +149,7 @@ PlatformMemMapInitialization ( return; } - TopOfLowRam = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); PciExBarBase = 0; if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { // @@ -158,11 +157,11 @@ PlatformMemMapInitialization ( // the base of the 32-bit PCI host aperture. // PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress); - ASSERT (TopOfLowRam <= PciExBarBase); + ASSERT (PlatformInfoHob->LowMemory <= PciExBarBase); ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); PciBase = (UINT32)(PciExBarBase + SIZE_256MB); } else { - ASSERT (TopOfLowRam <= PlatformInfoHob->Uc32Base); + ASSERT (PlatformInfoHob->LowMemory <= PlatformInfoHob->Uc32Base); PciBase = PlatformInfoHob->Uc32Base; } diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index 3d8375320dcb..41d186986ba8 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -271,7 +271,8 @@ PublishPeiMemory ( UINT32 S3AcpiReservedMemoryBase; UINT32 S3AcpiReservedMemorySize; - LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + LowerMemorySize = PlatformInfoHob->LowMemory; if (PlatformInfoHob->SmmSmramRequire) { // // TSEG is chipped from the end of low RAM -- 2.39.0