From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.groups.io with SMTP id smtpd.web10.18117.1673422170011789862 for ; Tue, 10 Jan 2023 23:29:30 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=g/nfnFcP; spf=pass (domain: redhat.com, ip: 170.10.133.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673422168; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=pRj7KnGEydhL0oMiMfLTkyFsDAyoJxEJ2JejqwG9QRo=; b=g/nfnFcPPtXppZYoy30VYCoJaeKO2wBxpbhAx91bZkKhNNA1ku9KgV63bWXsO/iaX3ADGI dZD4V8WMuR4dsxhM2LES0jC52O5eDVAhkqKE00vbZK0j4/5NL8UEFxRZgwvgNAkusQOlc2 42S5xJK03sRrgn5GLfGhHPXp2Z1UZ/g= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-526-J6uZ2aP4PU2VPxLFlxIsnw-1; Wed, 11 Jan 2023 02:29:27 -0500 X-MC-Unique: J6uZ2aP4PU2VPxLFlxIsnw-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id EF4DC85CBE0; Wed, 11 Jan 2023 07:29:26 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.238]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 909171121314; Wed, 11 Jan 2023 07:29:26 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 36DD1180060E; Wed, 11 Jan 2023 08:29:25 +0100 (CET) Date: Wed, 11 Jan 2023 08:29:25 +0100 From: "Gerd Hoffmann" To: Laszlo Ersek Cc: devel@edk2.groups.io, Pawel Polawski , Jiewen Yao , Oliver Steffen , Jordan Justen , Ard Biesheuvel Subject: Re: [PATCH v2 2/4] OvmfPkg/PlatformInitLib: Add PlatformGetLowMemoryCB Message-ID: <20230111072925.l47t4ahgynqjyegq@sirius.home.kraxel.org> References: <20230110082123.159521-1-kraxel@redhat.com> <20230110082123.159521-3-kraxel@redhat.com> <043b03d6-0a6b-c533-255b-24a7805d5cca@redhat.com> MIME-Version: 1.0 In-Reply-To: <043b03d6-0a6b-c533-255b-24a7805d5cca@redhat.com> X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline > > + Candidate = E820Entry->BaseAddr + E820Entry->Length; > > + if (Candidate >= BASE_4GB) { > > + return; > > + } > (1) This looks like a faithful conversion / extraction, but I'd vaguely > noticed something earlier, in the original code. Namely, when the > exclusive end of the range is exactly 4GB, that should still qualify as > low memory, shouldn't it? > > Not that it matters in practice, because just below 4GB, we'll never > ever have RAM on QEMU (pc or q35 -- I think even microvm, too). Yes. > But, for clarity, changing the limit condition as a separate patch > (afterwards) might make sense. Well, BASE_4GB-1 fits into LowMemory (which is UINT32) whereas BASE_4GB does not ... > > - return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE); > > + PlatformInfoHob->LowMemory = GetHighestSystemMemoryAddressFromPvhMemmap (TRUE); > (2) Here you are converting a UINT64 from > GetHighestSystemMemoryAddressFromPvhMemmap() to UINT32; I think that > might trip up some MSVC compilers. I suggest preserving the cast. OK. > PlatformInfoHob->LowMemory = 0; > (I realize the platform info HOB could be zero-filled upon allocation -- > but then at least for consistency with the 4GB+ search initialization, a > comment could be justified.) It's explicitly cleared with ZeroMem (in BuildPlatformInfoHob), so there is no zero-initialize LowMemory again. > > diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c > > index 3d8375320dcb..41d186986ba8 100644 > > --- a/OvmfPkg/PlatformPei/MemDetect.c > > +++ b/OvmfPkg/PlatformPei/MemDetect.c > > @@ -271,7 +271,8 @@ PublishPeiMemory ( > > UINT32 S3AcpiReservedMemoryBase; > > UINT32 S3AcpiReservedMemorySize; > > > > - LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); > > + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); > > + LowerMemorySize = PlatformInfoHob->LowMemory; > > if (PlatformInfoHob->SmmSmramRequire) { > > // > > // TSEG is chipped from the end of low RAM > > So I really like how small this hunk is, and I wondered why it differed > so much from the rest, where you removed the local variables. > > I understand now: because PublishPeiMemory() actually modifies > "LowerMemorySize" in multiple steps. OK then, I see both points; here we > need to keep "LowerMemorySize", because we can't modify the platform > info HOB; but in the rest of the hunks, it's better if we just remove > the useless locals. OK. Yes, that is the pattern. LowMemory holds the memory installed. PublishPeiMemory calculates how edk2 uses that memory, which is something different. > code duplication is causing some churn for the present patch. I suggest > reordering the branches as follows: > > - microvm: do nothing, just return > - cloudhv: constant assignments, then return > - grab LowerMemorySize -- commonly needed for the rest! > - handle q35 > - handle i440fx as default / fallback. Makes sense indeed. > (9) BTW, still regarding commit 2a0bd3bffc80 ("OvmfPkg/PlatformInitLib: > q35 mtrr setup fix", 2022-09-28) -- does the following code comment > still apply? > > // > // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI > // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable. > // > > Because, in case the new branch introduced by commit 2a0bd3bffc80 takes > effect (namely, "Uc32Base = BASE_2GB"), I'm not sure where the PCIEXBAR > starts, and then the above comment may no longer hold. PCIEXBAR location doesn't change, it's still at 0xb0000000. > > ZeroMem (&PlatformInfoHob, sizeof (PlatformInfoHob)); > > + PlatformGetSystemMemorySizeBelow4gb (&PlatformInfoHob); > > PlatformInfoHob.HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID); > > - LowMemorySize = PlatformGetSystemMemorySizeBelow4gb (&PlatformInfoHob); > > + LowMemorySize = PlatformInfoHob.LowMemory; > > ASSERT (LowMemorySize != 0); > > LowMemoryStart = FixedPcdGet32 (PcdOvmfDxeMemFvBase) + FixedPcdGet32 (PcdOvmfDxeMemFvSize); > > LowMemorySize -= LowMemoryStart; > > (10) I think this PlatformGetSystemMemorySizeBelow4gb() call is not > placed correctly. > > PlatformGetSystemMemorySizeBelow4gb() depends on "HostBridgeDevId", but > this hunk reorders the setting of "HostBridgeDevId" against the call to > PlatformGetSystemMemorySizeBelow4gb(). Correct, nice catch. Placed it there for optical reasons (keep the nice '=' alignment) but didn't realize that. > > diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/PlatformInitLib/Platform.c > > index 3e13c5d4b34f..9ab0342fd8c0 100644 > > --- a/OvmfPkg/Library/PlatformInitLib/Platform.c > > +++ b/OvmfPkg/Library/PlatformInitLib/Platform.c > > @@ -128,7 +128,6 @@ PlatformMemMapInitialization ( > > { > > UINT64 PciIoBase; > > UINT64 PciIoSize; > > - UINT32 TopOfLowRam; > > UINT64 PciExBarBase; > > UINT32 PciBase; > > UINT32 PciSize; > > @@ -150,7 +149,7 @@ PlatformMemMapInitialization ( > > return; > > } > > > > - TopOfLowRam = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); > > + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); > > PciExBarBase = 0; > > if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { > > // > > @@ -158,11 +157,11 @@ PlatformMemMapInitialization ( > > // the base of the 32-bit PCI host aperture. > > // > > PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress); > > - ASSERT (TopOfLowRam <= PciExBarBase); > > + ASSERT (PlatformInfoHob->LowMemory <= PciExBarBase); > > ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); > > PciBase = (UINT32)(PciExBarBase + SIZE_256MB); > > This change looks OK, but, similarly to my question (9): > > (11) Is the following comment still up to date: > > // > // The MMCONFIG area is expected to fall between the top of low RAM and > // the base of the 32-bit PCI host aperture. > // > > with regard to the new branch introduced by commit 2a0bd3bffc80 > ("OvmfPkg/PlatformInitLib: q35 mtrr setup fix", 2022-09-28)? root@fedora ~# cat /proc/iomem [ ... ] 7ebfe000-7effffff : System RAM 7f000000-7fffffff : Reserved 80000000-afffffff : PCI Bus 0000:00 b0000000-bfffffff : PCI MMCONFIG 0000 [bus 00-ff] b0000000-bfffffff : Reserved b0000000-bfffffff : pnp 00:04 c0000000-febfffff : PCI Bus 0000:00 [ ... ] root@fedora ~# cat /proc/mtrr reg00: base=0x080000000 ( 2048MB), size= 2048MB, count=1: uncachable reg01: base=0x800000000 (32768MB), size=32768MB, count=1: uncachable With gigabyte-alignment being the common case these days it might make sense to place the MMCONFIG area at 0xe0000000 instead ... take care, Gerd