From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.groups.io with SMTP id smtpd.web10.50848.1673516069897899752 for ; Thu, 12 Jan 2023 01:34:30 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=aVL3bdK7; spf=pass (domain: redhat.com, ip: 170.10.129.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673516069; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/VXEjToyh1oc2q4VEKKd9KQ+4eUtLjwDX33h0iBEcLQ=; b=aVL3bdK7/S82Kcpd6M+TrHHtXfddQrkjbZ2ioHWcj6X19UfyMx35Pau6MICuaRKTqsj0/n EpkH2vyepHUVKxk3f63FNbBZAUmW0LjyEH3e4VKBleLgx1twrqS7u+PfxxInQzHg4wIuTT JJF72vjBJx8P0O1omUnu2g3dlDPHqcM= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-479-pW0ZpI0VM1OLw0PAGjJklA-1; Thu, 12 Jan 2023 04:34:27 -0500 X-MC-Unique: pW0ZpI0VM1OLw0PAGjJklA-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 49B523C10ED2; Thu, 12 Jan 2023 09:34:27 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.238]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D15BE2026D68; Thu, 12 Jan 2023 09:34:26 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 812281800936; Thu, 12 Jan 2023 10:34:25 +0100 (CET) From: "Gerd Hoffmann" To: devel@edk2.groups.io Cc: Oliver Steffen , =?UTF-8?q?L=C3=A1szl=C3=B3=20=C3=89rsek?= , Ard Biesheuvel , Jordan Justen , Pawel Polawski , Jiewen Yao , Gerd Hoffmann Subject: [PATCH v3 1/8] OvmfPkg/PlatformInitLib: Add PlatformScanE820 and GetFirstNonAddressCB Date: Thu, 12 Jan 2023 10:34:18 +0100 Message-Id: <20230112093425.1228300-2-kraxel@redhat.com> In-Reply-To: <20230112093425.1228300-1-kraxel@redhat.com> References: <20230112093425.1228300-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true First step replacing the PlatformScanOrAdd64BitE820Ram() function. Add a PlatformScanE820() function which loops over the e280 entries from FwCfg and calls a callback for each of them. Add a GetFirstNonAddressCB() function which will store the first free address (right after the last RAM block) in PlatformInfoHob->FirstNonAddress. This replaces calls to PlatformScanOrAdd64BitE820Ram() with non-NULL MaxAddress. Write any actions done (setting FirstNonAddress) to the firmware log with INFO loglevel. Also drop local FirstNonAddress variables and use PlatformInfoHob->FirstNonAddress instead everywhere. Signed-off-by: Gerd Hoffmann --- OvmfPkg/Library/PlatformInitLib/MemDetect.c | 115 ++++++++++++++++---- 1 file changed, 92 insertions(+), 23 deletions(-) diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/PlatformInitLib/MemDetect.c index 0c4956852689..dd98622de561 100644 --- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c @@ -251,6 +251,83 @@ PlatformScanOrAdd64BitE820Ram ( return EFI_SUCCESS; } +typedef VOID (*E820_SCAN_CALLBACK) ( + EFI_E820_ENTRY64 *E820Entry, + EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + +/** + Store first address not used by e820 RAM entries in + PlatformInfoHob->FirstNonAddress +**/ +VOID +PlatformGetFirstNonAddressCB ( + IN EFI_E820_ENTRY64 *E820Entry, + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + UINT64 Candidate; + + if (E820Entry->Type != EfiAcpiAddressRangeMemory) { + return; + } + + Candidate = E820Entry->BaseAddr + E820Entry->Length; + if (PlatformInfoHob->FirstNonAddress < Candidate) { + DEBUG ((DEBUG_INFO, "%a: FirstNonAddress=0x%Lx\n", __FUNCTION__, Candidate)); + PlatformInfoHob->FirstNonAddress = Candidate; + } +} + +/** + Iterate over the entries in QEMU's fw_cfg E820 RAM map, call the + passed callback for each entry. + + @param[in] Callback The callback function to be called. + + @param[in out] PlatformInfoHob PlatformInfo struct which is passed + through to the callback. + + @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed. + + @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a + whole multiple of sizeof(EFI_E820_ENTRY64). No + RAM entry was processed. + + @return Error codes from QemuFwCfgFindFile(). No RAM + entry was processed. +**/ +STATIC +EFI_STATUS +PlatformScanE820 ( + IN E820_SCAN_CALLBACK Callback, + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + EFI_STATUS Status; + FIRMWARE_CONFIG_ITEM FwCfgItem; + UINTN FwCfgSize; + EFI_E820_ENTRY64 E820Entry; + UINTN Processed; + + Status = QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize); + if (EFI_ERROR (Status)) { + return Status; + } + + if (FwCfgSize % sizeof E820Entry != 0) { + return EFI_PROTOCOL_ERROR; + } + + QemuFwCfgSelectItem (FwCfgItem); + for (Processed = 0; Processed < FwCfgSize; Processed += sizeof E820Entry) { + QemuFwCfgReadBytes (sizeof E820Entry, &E820Entry); + Callback (&E820Entry, PlatformInfoHob); + } + + return EFI_SUCCESS; +} + /** Returns PVH memmap @@ -384,23 +461,17 @@ PlatformGetSystemMemorySizeAbove4gb ( Return the highest address that DXE could possibly use, plus one. **/ STATIC -UINT64 +VOID PlatformGetFirstNonAddress ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - UINT64 FirstNonAddress; UINT32 FwCfgPciMmio64Mb; EFI_STATUS Status; FIRMWARE_CONFIG_ITEM FwCfgItem; UINTN FwCfgSize; UINT64 HotPlugMemoryEnd; - // - // set FirstNonAddress to suppress incorrect compiler/analyzer warnings - // - FirstNonAddress = 0; - // // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM // address from it. This can express an address >= 4GB+1TB. @@ -408,9 +479,10 @@ PlatformGetFirstNonAddress ( // Otherwise, get the flat size of the memory above 4GB from the CMOS (which // can only express a size smaller than 1TB), and add it to 4GB. // - Status = PlatformScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress); + PlatformInfoHob->FirstNonAddress = BASE_4GB; + Status = PlatformScanE820 (PlatformGetFirstNonAddressCB, PlatformInfoHob); if (EFI_ERROR (Status)) { - FirstNonAddress = BASE_4GB + PlatformGetSystemMemorySizeAbove4gb (); + PlatformInfoHob->FirstNonAddress = BASE_4GB + PlatformGetSystemMemorySizeAbove4gb (); } // @@ -420,7 +492,7 @@ PlatformGetFirstNonAddress ( // #ifdef MDE_CPU_IA32 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) { - return FirstNonAddress; + return; } #endif @@ -473,7 +545,7 @@ PlatformGetFirstNonAddress ( // determines the highest address plus one. The memory hotplug area (see // below) plays no role for the firmware in this case. // - return FirstNonAddress; + return; } // @@ -497,15 +569,15 @@ PlatformGetFirstNonAddress ( HotPlugMemoryEnd )); - ASSERT (HotPlugMemoryEnd >= FirstNonAddress); - FirstNonAddress = HotPlugMemoryEnd; + ASSERT (HotPlugMemoryEnd >= PlatformInfoHob->FirstNonAddress); + PlatformInfoHob->FirstNonAddress = HotPlugMemoryEnd; } // // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so // that the host can map it with 1GB hugepages. Follow suit. // - PlatformInfoHob->PcdPciMmio64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB); + PlatformInfoHob->PcdPciMmio64Base = ALIGN_VALUE (PlatformInfoHob->FirstNonAddress, (UINT64)SIZE_1GB); PlatformInfoHob->PcdPciMmio64Size = ALIGN_VALUE (PlatformInfoHob->PcdPciMmio64Size, (UINT64)SIZE_1GB); // @@ -519,8 +591,8 @@ PlatformGetFirstNonAddress ( // // The useful address space ends with the 64-bit PCI host aperture. // - FirstNonAddress = PlatformInfoHob->PcdPciMmio64Base + PlatformInfoHob->PcdPciMmio64Size; - return FirstNonAddress; + PlatformInfoHob->FirstNonAddress = PlatformInfoHob->PcdPciMmio64Base + PlatformInfoHob->PcdPciMmio64Size; + return; } /* @@ -781,7 +853,6 @@ PlatformAddressWidthInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - UINT64 FirstNonAddress; UINT8 PhysMemAddressWidth; EFI_STATUS Status; @@ -794,7 +865,7 @@ PlatformAddressWidthInitialization ( // First scan host-provided hardware information to assess if the address // space is already known. If so, guest must use those values. // - Status = PlatformScanHostProvided64BitPciMmioEnd (&FirstNonAddress); + Status = PlatformScanHostProvided64BitPciMmioEnd (&PlatformInfoHob->FirstNonAddress); if (EFI_ERROR (Status)) { // @@ -806,13 +877,12 @@ PlatformAddressWidthInitialization ( // The DXL IPL keys off of the physical address bits advertized in the CPU // HOB. To conserve memory, we calculate the minimum address width here. // - FirstNonAddress = PlatformGetFirstNonAddress (PlatformInfoHob); + PlatformGetFirstNonAddress (PlatformInfoHob); } PlatformAddressWidthFromCpuid (PlatformInfoHob, TRUE); if (PlatformInfoHob->PhysMemAddressWidth != 0) { // physical address width is known - PlatformInfoHob->FirstNonAddress = FirstNonAddress; PlatformDynamicMmioWindow (PlatformInfoHob); return; } @@ -823,13 +893,13 @@ PlatformAddressWidthInitialization ( // -> try be conservstibe to stay below the guaranteed minimum of // 36 phys bits (aka 64 GB). // - PhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress); + PhysMemAddressWidth = (UINT8)HighBitSet64 (PlatformInfoHob->FirstNonAddress); // // If FirstNonAddress is not an integral power of two, then we need an // additional bit. // - if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) { + if ((PlatformInfoHob->FirstNonAddress & (PlatformInfoHob->FirstNonAddress - 1)) != 0) { ++PhysMemAddressWidth; } @@ -857,7 +927,6 @@ PlatformAddressWidthInitialization ( ASSERT (PhysMemAddressWidth <= 48); #endif - PlatformInfoHob->FirstNonAddress = FirstNonAddress; PlatformInfoHob->PhysMemAddressWidth = PhysMemAddressWidth; } -- 2.39.0