From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.80768.1673594263982383415 for ; Thu, 12 Jan 2023 23:17:46 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=V0IaVLSV; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673594266; x=1705130266; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=4wpG0zrsTRvvlLr9WwbqydtX8xtgO1mzZ04F2pvBbfM=; b=V0IaVLSVAnw5ekzU08mhwluv3CjZFXjF8/BSXE40vWYzxC0wQqdDEErL rlX+wCymbC8LROwvN5wvRZLNfh5y9JdAVBf7zb9mQumY2C+IqvPLwn79J Z2k7vqhRmEHdLa7GCg7B/FUpVbZnIOZZBHAVdoOzUXDcPiuVXH4K6R6NZ 2cV+y5ZTYvGagCV4voevEp7eAJOJKAcefvJFr4R7dO8ciV0mA1ImLju69 aGUEehrmFFFY8qX5VwjWUOfxfVLK8jOW4KUO34gOws+C5D6Tq6IeqdAvl vOFsyg9joRzyKO4hUJ1ji905n240MWelmkiv4svjYJ17i543b+d9QnRZU g==; X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="410169722" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="410169722" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 23:17:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="688646177" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="688646177" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga008.jf.intel.com with ESMTP; 12 Jan 2023 23:17:43 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [PATCH v1 1/4] UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB Data Date: Fri, 13 Jan 2023 15:17:35 +0800 Message-Id: <20230113071738.15868-2-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20230113071738.15868-1-jiaxin.wu@intel.com> References: <20230113071738.15868-1-jiaxin.wu@intel.com> The Smm Base HOB is used to store the relocated SmBase in array for each Processors. If gSmmBaseHobGuid produced, indicate SmBase for each Processors have been relocated. The SmBase address in hob can be guaranteed the SMRAM state save areas for all processors do not overlap. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Include/Guid/SmmBaseHob.h | 51 ++++++++++++++++++++++++++++++++++++ UefiCpuPkg/UefiCpuPkg.dec | 3 +++ 2 files changed, 54 insertions(+) create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h b/UefiCpuPkg/Include/Guid/SmmBaseHob.h new file mode 100644 index 0000000000..090b22a274 --- /dev/null +++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h @@ -0,0 +1,51 @@ +/** @file + The Smm Base HOB is used to store the information of: + * The relocated SmBase in array for each Processors. + + If gSmmBaseHobGuid produced, indicate SmBase for each Processors + have been relocated and SmBase in HOB can be guaranteed the SMRAM + state save areas for all processors do not overlap. SMM CPU driver + should retrieve the SMBASE addresses from this HOB and installs the + SMI handler at [SMBASE+8000h] for each processor instead of relocating + SMM Base addresses from SMRAM again. + + With SMM Base Hob, SMM CPU driver doesn't need the RSM instruction + to reload the SMBASE register with the new allocated value in SMBASE + field each time it exits SMM. SMBASE Register for each processors + have already been programmed in parallel since the same default + SMBASE Address (0x30000) is not used, thus the CPUs over-writing + each other's SMM Save State Area will not happen. This way will save + boot time on multi-core system. + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_BASE_HOB_H_ +#define SMM_BASE_HOB_H_ + +#include +#include + +#define SMM_BASE_HOB_DATA_GUID \ + { \ + 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73} \ + } + +#pragma pack(1) +typedef struct { + /// + /// Describes the Number of all max supported processors. + /// + UINT64 NumberOfProcessors; + /// + /// Pointer to SmBase address for each Processors. + /// + UINT64 SmBase[]; +} SMM_BASE_HOB_DATA; +#pragma pack() + +extern EFI_GUID gSmmBaseHobGuid; + +#endif diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index cff239d528..2afd08cdd2 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -76,10 +76,13 @@ gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }} ## Include/Guid/MicrocodePatchHob.h gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }} + ## Include/Guid/SmmBaseHob.h + gSmmBaseHobGuid = { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73 }} + [Protocols] ## Include/Protocol/SmmCpuService.h gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }} gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }} -- 2.16.2.windows.1