From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.80768.1673594263982383415 for ; Thu, 12 Jan 2023 23:17:48 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=HULFUJMB; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673594268; x=1705130268; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=GNem9icrpZJDMHIcLKcmnOoxULOHQ5A4QayhylWylIg=; b=HULFUJMB5irG/wVNMn3wJmeJND5hMQVz9rfriQG9sdumXCLT5mC6YKPC 6Y4xgE1qdgpWQvT+DdwSm2tmYkTe/fzEHy/egihQK7rH10192k7TfCvFn uhNbh0mms6sSV5Wv/Yvne9D1MQs2I1ZybDCvLSl8IQCD7suIALHfLRtte J5lClCa0Ng+0nmyEbtKzV55QF4fwKHvEByI2d4d9+LtWSrpx9S80DP9Tv H0Q37DSL4t8rZEEPUAmw/1LsivM+cmW/1jl5CcUAF76+KSeymlez9T86j cetqW18aMeaXE62AAxMaWZtqcmsdIxgXYUOy4zCwRA2KcI7VcckTkCIGL g==; X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="410169748" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="410169748" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 23:17:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="688646193" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="688646193" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga008.jf.intel.com with ESMTP; 12 Jan 2023 23:17:45 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [PATCH v1 2/4] UefiCpuPkg/PiSmmCpuDxeSmm: Consume SMM Base Hob for SmBase info Date: Fri, 13 Jan 2023 15:17:36 +0800 Message-Id: <20230113071738.15868-3-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20230113071738.15868-1-jiaxin.wu@intel.com> References: <20230113071738.15868-1-jiaxin.wu@intel.com> SMM CPU driver will retrieve the SMBASE addresses from SMM Base Hob and installs the SMI handler at [SMBASE+8000h] for each processor instead of relocating SMM Base addresses from SMRAM again. With SMM Base Hob, SMM CPU driver does not need the RSM instruction to reload the SMBASE register with the new allocated value in SMBASE field each time it exits SMM. SMBASE Register for each processors have already been programmed in parallel since the same default SMBASE Address(0x30000) is not used, thus the CPUs over-writing each other's SMM Save State Area will not happen. This way will save boot time on multi-core system. Mainly changes as below: *Combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one (gcSmiHandlerTemplate), the new SMI handler needs to run to 2 paths: one to SmmCpuFeaturesInitializeProcessor(), the other to SMM Core Entry Point. *Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM init before normal SMI sources happen. *Call SmmCpuFeaturesInitializeProcessor() in parallel. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 40 ++++++- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 25 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 155 ++++++++++++++++++++------- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 21 +++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + 5 files changed, 197 insertions(+), 45 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c index fb4a44eab6..f7479fc74d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -765,10 +765,11 @@ SmmRestoreCpu ( SMM_S3_RESUME_STATE *SmmS3ResumeState; IA32_DESCRIPTOR Ia32Idtr; IA32_DESCRIPTOR X64Idtr; IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER]; EFI_STATUS Status; + UINTN Index; DEBUG ((DEBUG_INFO, "SmmRestoreCpu()\n")); mSmmS3Flag = TRUE; @@ -822,13 +823,48 @@ SmmRestoreCpu ( // InitializeCpuBeforeRebase (); } // - // Restore SMBASE for BSP and all APs + // Retrive the allocated SmmBase from gSmmBaseHobGuid. If found, + // means the SmBase relocation has been done. + // + if (GetFirstGuidHob (&gSmmBaseHobGuid) != NULL) { + mSmBaseRelocationDone = TRUE; + } else { + mSmBaseRelocationDone = FALSE; + } + + // + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! // - SmmRelocateBases (); + if (!mSmBaseRelocationDone) { + // + // Restore SMBASE for BSP and all APs + // + SmmRelocateBases (); + } else { + mSmmInitialized = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus); + ASSERT (mSmmInitialized != NULL); + + mBspApicId = GetApicId (); + + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM init + // + SendSmiIpi (mBspApicId); + SendSmiIpiAllExcludingSelf (); + + // + // Wait for all processors to finish its 1st SMI + // + for (Index = 0; Index < mNumberOfCpus; Index++) { + while (mSmmInitialized[Index] == FALSE) { + } + } + } // // Skip initialization if mAcpiCpuData is not valid // if (mAcpiCpuData.NumberOfCpus > 0) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index a0967eb69c..b4339eef48 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1728,10 +1728,29 @@ SmiRendezvous ( // when using on-demand paging for above 4G memory. // Cr2 = 0; SaveCr2 (&Cr2); + if (mSmBaseRelocationDone && !mSmmInitialized[CpuIndex]) { + // + // Perform SmmInitHandler for CpuIndex + // + SmmInitHandler (); + + // + // Restore Cr2 + // + RestoreCr2 (Cr2); + + // + // Mark the first SMI init for CpuIndex has been done so as to avoid the reentry. + // + mSmmInitialized[CpuIndex] = TRUE; + + return; + } + // // Call the user register Startup function first. // if (mSmmMpSyncData->StartupProcedure != NULL) { mSmmMpSyncData->StartupProcedure (mSmmMpSyncData->StartupProcArgs); @@ -1882,13 +1901,13 @@ Exit: // RestoreCr2 (Cr2); } /** - Initialize PackageBsp Info. Processor specified by mPackageFirstThreadIndex[PackageIndex] - will do the package-scope register programming. Set default CpuIndex to (UINT32)-1, which - means not specified yet. + Initialize mPackageFirstThreadIndex Info. Processor specified by mPackageFirstThreadIndex[PackageIndex] + will do the package-scope register programming. Set default CpuIndex to (UINT32)-1, which means not + specified yet. **/ VOID InitPackageFirstThreadIndexInfo ( VOID diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c index 655175a2c6..aa1700ba58 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -83,10 +83,14 @@ EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = { EdkiiSmmClearMemoryAttributes }; EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER]; +BOOLEAN mSmBaseRelocationDone = FALSE; +BOOLEAN *mSmmInitialized = NULL; +UINT32 mBspApicId = 0; + // // SMM stack information // UINTN mSmmStackArrayBase; UINTN mSmmStackArrayEnd; @@ -341,29 +345,38 @@ VOID EFIAPI SmmInitHandler ( VOID ) { - UINT32 ApicId; - UINTN Index; + UINT32 ApicId; + UINTN Index; + BOOLEAN IsMonarch; + + IsMonarch = FALSE; // // Update SMM IDT entries' code segment and load IDT // AsmWriteIdtr (&gcSmiIdtr); ApicId = GetApicId (); ASSERT (mNumberOfCpus <= mMaxNumberOfCpus); + if (!mSmBaseRelocationDone) { + IsMonarch = mIsBsp; + } else if (mBspApicId == ApicId) { + IsMonarch = TRUE; + } + for (Index = 0; Index < mNumberOfCpus; Index++) { if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) { // // Initialize SMM specific features on the currently executing CPU // SmmCpuFeaturesInitializeProcessor ( Index, - mIsBsp, + IsMonarch, gSmmCpuPrivate->ProcessorInfo, &mCpuHotPlugData ); if (!mSmmS3Flag) { @@ -371,23 +384,25 @@ SmmInitHandler ( // Check XD and BTS features on each processor on normal boot // CheckFeatureSupported (); } - if (mIsBsp) { + if (!mSmBaseRelocationDone) { + if (mIsBsp) { + // + // BSP rebase is already done above. + // Initialize private data during S3 resume + // + InitializeMpSyncData (); + } + // - // BSP rebase is already done above. - // Initialize private data during S3 resume + // Hook return after RSM to set SMM re-based flag // - InitializeMpSyncData (); + SemaphoreHook (Index, &mRebased[Index]); } - // - // Hook return after RSM to set SMM re-based flag - // - SemaphoreHook (Index, &mRebased[Index]); - return; } } ASSERT (FALSE); @@ -561,10 +576,15 @@ PiCpuSmmEntry ( UINT32 RegEcx; UINT32 RegEdx; UINTN FamilyId; UINTN ModelId; UINT32 Cr3; + EFI_HOB_GUID_TYPE *GuidHob; + SMM_BASE_HOB_DATA *SmmBaseHobData; + + GuidHob = NULL; + SmmBaseHobData = NULL; // // Initialize address fixup // PiSmmCpuSmmInitFixupAddress (); @@ -789,30 +809,52 @@ PiCpuSmmEntry ( // context must be reduced. // ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET)); // - // Allocate buffer for all of the tiles. + // Check whether the Required TileSize is enough. // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 34.11 SMBASE Relocation - // For Pentium and Intel486 processors, the SMBASE values must be - // aligned on a 32-KByte boundary or the processor will enter shutdown - // state during the execution of a RSM instruction. + if (TileSize > SIZE_8KB) { + DEBUG ((DEBUG_ERROR, "The Range of Smbase in SMRAM is not enough -- Required TileSize = 0x%08x, Actual TileSize = 0x%08x\n", TileSize, SIZE_8KB)); + ASSERT (TileSize <= SIZE_8KB); + return RETURN_BUFFER_TOO_SMALL; + } + // - // Intel486 processors: FamilyId is 4 - // Pentium processors : FamilyId is 5 + // Retrive the allocated SmmBase from gSmmBaseHobGuid. If found, + // means the SmBase relocation has been done. // - BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1)); - if ((FamilyId == 4) || (FamilyId == 5)) { - Buffer = AllocateAlignedCodePages (BufferPages, SIZE_32KB); + GuidHob = GetFirstGuidHob (&gSmmBaseHobGuid); + if (GuidHob != NULL) { + SmmBaseHobData = GET_GUID_HOB_DATA (GuidHob); + + ASSERT (SmmBaseHobData->NumberOfProcessors == mMaxNumberOfCpus); + mSmBaseRelocationDone = TRUE; } else { - Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB); - } + DEBUG ((DEBUG_INFO, "PiCpuSmmEntry: gSmmBaseHobGuid not found!\n")); + // + // Allocate buffer for all of the tiles. + // + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 34.11 SMBASE Relocation + // For Pentium and Intel486 processors, the SMBASE values must be + // aligned on a 32-KByte boundary or the processor will enter shutdown + // state during the execution of a RSM instruction. + // + // Intel486 processors: FamilyId is 4 + // Pentium processors : FamilyId is 5 + // + BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1)); + if ((FamilyId == 4) || (FamilyId == 5)) { + Buffer = AllocateAlignedCodePages (BufferPages, SIZE_32KB); + } else { + Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB); + } - ASSERT (Buffer != NULL); - DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages))); + ASSERT (Buffer != NULL); + DEBUG ((DEBUG_INFO, "New Allcoated SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages))); + } // // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA. // gSmmCpuPrivate->ProcessorInfo = (EFI_PROCESSOR_INFORMATION *)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus); @@ -843,11 +885,12 @@ PiCpuSmmEntry ( // Retrieve APIC ID of each enabled processor from the MP Services protocol. // Also compute the SMBASE address, CPU Save State address, and CPU Save state // size for each CPU in the platform // for (Index = 0; Index < mMaxNumberOfCpus; Index++) { - mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET; + mCpuHotPlugData.SmBase[Index] = mSmBaseRelocationDone ? (UINTN)SmmBaseHobData->SmBase[Index] : (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET; + gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof (SMRAM_SAVE_STATE_MAP); gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); gSmmCpuPrivate->Operation[Index] = SmmCpuNone; if (Index < mNumberOfCpus) { @@ -956,21 +999,27 @@ PiCpuSmmEntry ( // Initialize IDT // InitializeSmmIdt (); // - // Relocate SMM Base addresses to the ones allocated from SMRAM + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! // - mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus); - ASSERT (mRebased != NULL); - SmmRelocateBases (); + if (!mSmBaseRelocationDone) { + // + // Relocate SMM Base addresses to the ones allocated from SMRAM + // + mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus); + ASSERT (mRebased != NULL); + SmmRelocateBases (); - // - // Call hook for BSP to perform extra actions in normal mode after all - // SMM base addresses have been relocated on all CPUs - // - SmmCpuFeaturesSmmRelocationComplete (); + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported)); // // SMM Time initialization @@ -997,10 +1046,42 @@ PiCpuSmmEntry ( ); } } } + // + // For relocated SMBASE, some MSRs & CSRs are still required to be configured in SMM Mode for SMM Initialization. + // Those MSRs & CSRs must be configured before normal SMI sources happen. + // So, here is to issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM init + // + if (mSmBaseRelocationDone) { + mSmmInitialized = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus); + ASSERT (mSmmInitialized != NULL); + + mBspApicId = GetApicId (); + + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM init + // + SendSmiIpi (mBspApicId); + SendSmiIpiAllExcludingSelf (); + + // + // Wait for all processors to finish its 1st SMI + // + for (Index = 0; Index < mNumberOfCpus; Index++) { + while (mSmmInitialized[Index] == FALSE) { + } + } + + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } + // // Fill in SMM Reserved Regions // gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart = 0; gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize = 0; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index 5f0a38e400..da6804c58b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -23,10 +23,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include #include +#include #include #include #include #include @@ -346,10 +347,20 @@ SmmWriteSaveState ( IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN CpuIndex, IN CONST VOID *Buffer ); +/** + C function for SMI handler. To change all processor's SMMBase Register. + +**/ +VOID +EFIAPI +SmmInitHandler ( + VOID + ); + /** Read a CPU Save State register on the target processor. This function abstracts the differences that whether the CPU Save State register is in the IA32 CPU Save State Map or X64 CPU Save State Map. @@ -400,10 +411,14 @@ WriteSaveStateRegister ( IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, IN CONST VOID *Buffer ); +extern BOOLEAN mSmBaseRelocationDone; +extern BOOLEAN *mSmmInitialized; +extern UINT32 mBspApicId; + extern CONST UINT8 gcSmmInitTemplate[]; extern CONST UINT16 gcSmmInitSize; X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0; extern UINT32 mSmmCr0; X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3; @@ -1486,13 +1501,13 @@ RegisterStartupProcedure ( IN EFI_AP_PROCEDURE Procedure, IN OUT VOID *ProcedureArguments OPTIONAL ); /** - Initialize PackageBsp Info. Processor specified by mPackageFirstThreadIndex[PackageIndex] - will do the package-scope register programming. Set default CpuIndex to (UINT32)-1, which - means not specified yet. + Initialize mPackageFirstThreadIndex Info. Processor specified by mPackageFirstThreadIndex[PackageIndex] + will do the package-scope register programming. Set default CpuIndex to (UINT32)-1, which means not + specified yet. **/ VOID InitPackageFirstThreadIndexInfo ( VOID diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf index b4b327f60c..6dbed17b96 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -112,10 +112,11 @@ [Guids] gEfiAcpiVariableGuid ## SOMETIMES_CONSUMES ## HOB # it is used for S3 boot. gEdkiiPiSmmMemoryAttributesTableGuid ## CONSUMES ## SystemTable gEfiMemoryAttributesTableGuid ## CONSUMES ## SystemTable + gSmmBaseHobGuid ## CONSUMES [FeaturePcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug ## CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp ## CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection ## CONSUMES -- 2.16.2.windows.1