From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.81431.1673598176394117495 for ; Fri, 13 Jan 2023 00:22:56 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=ZpeQtv4p; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: william2.wang@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673598176; x=1705134176; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=MFLtRb9f1gFa45M96T24goyrwnWMd1f6ZaRdjXuLH50=; b=ZpeQtv4pc6V47L4QQ7KUb9Y+MACfmYHy50dETnQoWlmfAyepIg6EB+qC +b3rkZ3ARFAKS/c9onX9HvPaAwIKgZ3/xz4q9cFGotoewuah0W3Ev/rNs dxuquM37vEzLHcktT6elduhLa4u0TwFx5h5sBVgkBWzhU4+3B5oF+CaOa 3QjRm9NRV/iy1FjKap9KJXUwcBkTHhif1Rl/NYPMZmU5Efvk/hwWnICts +2h7hAZMdFMxQpaqOZK1eEd914j8cTUsz+XRg34qrBjCi5TMUtJGBivZj d6qGAxOzHtFIYlReW6+FzWtWLQs7vC+i3rYsW+bOHpz53JhCIhaCW9vp1 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="304325605" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="304325605" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jan 2023 00:22:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="746862333" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="746862333" Received: from william4-desk.gar.corp.intel.com ([10.5.215.176]) by FMSMGA003.fm.intel.com with ESMTP; 13 Jan 2023 00:22:30 -0800 From: william2.wang@intel.com To: devel@edk2.groups.io Cc: William2 Wang , Michael D Kinney , Liming Gao , Ray Ni , Donald Kuo , Chandana C Kumar Subject: [PATCH v2] Update Architecture MSR to follow latest SDM. Date: Fri, 13 Jan 2023 16:22:27 +0800 Message-Id: <20230113082227.821-1-william2.wang@intel.com> X-Mailer: git-send-email 2.34.1.windows.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable From: William2 Wang REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4263 Update Architecture MSR contains the MSR10A.BIT23 and MSR195.BIT2-0 for overclocking undervolt protection. Cc: Michael D Kinney Cc: Liming Gao Cc: Ray Ni Cc: Donald Kuo Cc: Chandana C Kumar --- MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 198 ++++++++++++++++++++ 1 file changed, 198 insertions(+) diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Incl= ude/Register/Intel/ArchitecturalMsr.h index 071a8c689c..f548b56672 100644 --- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h +++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h @@ -682,6 +682,149 @@ typedef union { UINT64 Uint64;=0D } MSR_IA32_MTRRCAP_REGISTER;=0D =0D +/**=0D + Enumeration of Architectural Features (R/O). If CPUID.(EAX=3D07H, ECX=3D= 0):EDX[29]=3D1.=0D +=0D + @param ECX IA32_ARCH_CAPABILITIES (0x0000010A)=0D + @param EAX Lower 32-bits of MSR value.=0D + Described by the type IA32_ARCH_CAPABILITIES_REGISTER.=0D + @param EDX Upper 32-bits of MSR value.=0D + Described by the type IA32_ARCH_CAPABILITIES_REGISTER.=0D +=0D + Example usage=0D + @code=0D + IA32_ARCH_CAPABILITIES_REGISTER Msr;=0D +=0D + Msr.Uint64 =3D AsmReadMsr64 (IA32_ARCH_CAPABILITIES);=0D + @endcode=0D + @note IA32_ARCH_CAPABILITIES is defined as IA32_ARCH_CAPABILITIES in SDM= .=0D +**/=0D +#define IA32_ARCH_CAPABILITIES 0x0000010A=0D +=0D +/**=0D + MSR information returned for MSR index #IA32_ARCH_CAPABILITIES=0D +**/=0D +typedef union {=0D + ///=0D + /// Individual bit fields=0D + ///=0D + struct {=0D + ///=0D + /// [Bits 0] RDCL_NO: The processor is not susceptible to Rogue Data = Cache Load (RDCL).=0D + ///=0D + UINT32 RDCL_NO : 1;=0D + ///=0D + /// [Bit 1] IBRS_ALL: The processor supports enhanced IBRS.=0D + ///=0D + UINT32 IBRS_ALL : 1;=0D + ///=0D + /// [Bit 2] RSBA: The processor supports RSB Alternate. Alternative br= anch predictors=0D + /// may be used by RET instructions when the RSB is empty. SW using re= tpoline may be=0D + /// affected by this behavior.=0D + ///=0D + UINT32 RSBA : 1;=0D + ///=0D + /// [Bit 3] SKIP_L1DFL_VMENTRY: A value of 1 indicates the hypervisor = need not flush the=0D + /// L1D on VM entry.=0D + ///=0D + UINT32 SKIP_L1DFL_VMENTRY : 1;=0D + ///=0D + /// [Bit 4] SSB_NO: Processor is not susceptible to Speculative Store = Bypass.=0D + ///=0D + UINT32 SSB_NO : 1;=0D + ///=0D + /// [Bit 5] MDS_NO: Processor is not susceptible to Microarchitectural= Data Sampling (MDS).=0D + ///=0D + UINT32 MDS_NO : 1;=0D + ///=0D + /// [Bit 6] IF_PSCHANGE_MC_NO: The processor is not susceptible to a m= achine check error due to=0D + /// modifying the size of a code page without TLB invalidation.=0D + ///=0D + UINT32 IF_PSCHANGE_MC_NO : 1;=0D + ///=0D + /// [Bit 7] TSX_CTRL: If 1, indicates presence of IA32_TSX_CTRL MSR.=0D + ///=0D + UINT32 TSX_CTRL : 1;=0D + ///=0D + /// [Bit 8] TAA_NO: If 1, processor is not affected by TAA.=0D + ///=0D + UINT32 TAA_NO : 1;=0D + UINT32 Reserved1 : 1;=0D + ///=0D + /// [Bit 10] MISC_PACKAGE_CTLS: The processor supports IA32_MISC_PACKA= GE_CTLS MSR.=0D + ///=0D + UINT32 MISC_PACKAGE_CTLS : 1;=0D + ///=0D + /// [Bit 11] ENERGY_FILTERING_CTL: The processor supports setting and = reading the=0D + /// IA32_MISC_PACKAGE_CTLS[0] (ENERGY_FILTERING_ENABLE) bit.=0D + ///=0D + UINT32 ENERGY_FILTERING_CTL : 1;=0D + ///=0D + /// [Bit 12] DOITM: If 1, the processor supports Data Operand Independ= ent Timing Mode.=0D + ///=0D + UINT32 DOITM : 1;=0D + ///=0D + /// [Bit 13] SBDR_SSDP_NO: The processor is not affected by either the= Shared Buffers Data=0D + /// Read (SBDR) vulnerability or the Sideband Stale Data Propagator (S= SDP).=0D + ///=0D + UINT32 SBDR_SSDP_NO : 1;=0D + ///=0D + /// [Bit 14] FBSDP_NO: The processor is not affected by the Fill Buffe= r Stale Data Propagator (FBSDP).=0D + ///=0D + UINT32 FBSDP_NO : 1;=0D + ///=0D + /// [Bit 15] PSDP_NO: The processor is not affected by vulnerabilities= involving the Primary Stale Data Propagator (PSDP).=0D + ///=0D + UINT32 PSDP_NO : 1;=0D + UINT32 Reserved2 : 1;=0D + ///=0D + /// [Bit 17] FB_CLEAR: If 1, the processor supports overwrite of fill = buffer values as part of MD_CLEAR operations=0D + /// with the VERW instruction.=0D + ///=0D + UINT32 FB_CLEAR : 1;=0D + ///=0D + /// [Bit 18] FB_CLEAR_CTRL: If 1, the processor supports the IA32_MCU_= OPT_CTRL MSR=0D + /// and allows software to set bit 3 of that MSR (FB_CLEAR_DIS).=0D + ///=0D + UINT32 FB_CLEAR_CTRL : 1;=0D + ///=0D + /// [Bit 19] RRSBA: A value of 1 indicates the processor may have the = RRSBA alternate prediction=0D + /// behavior, if not disabled by RRSBA_DIS_U or RRSBA_DIS_S.=0D + ///=0D + UINT32 RRSBA : 1;=0D + ///=0D + /// [Bit 20] BHI_NO: A value of 1 indicates BHI_NO branch prediction b= ehavior, regardless of=0D + /// the value of IA32_SPEC_CTRL[BHI_DIS_S] MSR bit.=0D + ///=0D + UINT32 BHI_NO : 1;=0D + //=0D + /// [Bit 21] XAPIC_DISABLE_STATUS: Enumerates that the IA32_XAPIC_DISA= BLE_STATUS MSR exists,=0D + /// and that bit 0 specifies whether the legacy xAPIC is disabled and = APIC state is locked to x2APIC.=0D + ///=0D + UINT32 XAPIC_DISABLE_STATUS : 1;=0D + UINT32 Reserved3 : 1;=0D + ///=0D + /// [Bit 23] OVERCLOCKING_STATUS: If set, the IA32_OVERCLOCKING_STATUS= MSR exists.=0D + ///=0D + UINT32 OVERCLOCKING_STATUS : 1;=0D + ///=0D + /// [Bit 24] PBRSB_NO: If 1, the processor is not affected by issues r= elated to Post-Barrier=0D + /// Return Stack Buffer Predictions.=0D + ///=0D + UINT32 PBRSB_NO : 1;=0D + UINT32 Reserved4 : 7;=0D + UINT32 Reserved5 : 32;=0D + } Bits;=0D + ///=0D + /// All bit fields as a 32-bit value=0D + ///=0D + UINT32 Uint32;=0D + ///=0D + /// All bit fields as a 64-bit value=0D + ///=0D + UINT64 Uint64;=0D +} IA32_ARCH_CAPABILITIES_REGISTER;=0D +=0D /**=0D SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_0= 1H.=0D =0D @@ -1035,6 +1178,61 @@ typedef union { UINT64 Uint64;=0D } MSR_IA32_PERFEVTSEL_REGISTER;=0D =0D +/**=0D + Overclocking Status (R/O) IA32_ARCH_CAPABILITIES[bit 23] enumerates supp= ort for this MSR.=0D +=0D + @param ECX IA32_OVERCLOCKING_STATUS (0x00000195)=0D + @param EAX Lower 32-bits of MSR value.=0D + Described by the type IA32_OVERCLOCKING_STATUS_REGISTER.=0D + @param EDX Upper 32-bits of MSR value.=0D + Described by the type IA32_OVERCLOCKING_STATUS_REGISTER.=0D +=0D + Example usage=0D + @code=0D + IA32_OVERCLOCKING_STATUS_REGISTER Msr;=0D +=0D + Msr.Uint64 =3D AsmReadMsr64 (IA32_OVERCLOCKING_STATUS);=0D + @endcode=0D + @note IA32_OVERCLOCKING_STATUS is defined as IA32_OVERCLOCKING_STATUS in= SDM.=0D +**/=0D +#define IA32_OVERCLOCKING_STATUS 0x00000195=0D +=0D +/**=0D + MSR information returned for MSR index #IA32_ARCH_CAPABILITIES=0D +**/=0D +typedef union {=0D + ///=0D + /// Individual bit fields=0D + ///=0D + struct {=0D + ///=0D + /// [Bits 0] Indicates if specific forms of overclocking have been en= abled on this boot or reset=0D + /// cycle: 0 indicates no, 1 indicates yes.=0D + ///=0D + UINT32 OverclockingUtilized : 1;=0D + ///=0D + /// [Bits 1] Indicates if the =E2=80=9CDynamic OC Undervolt Protectio= n=E2=80=9D security feature is active:=0D + /// 0 indicates disabled, 1 indicates enabled.=0D + ///=0D + UINT32 UndervoltProtection : 1;=0D + ///=0D + /// [Bits 2] Indicates that overclocking capabilities have been unloc= ked by BIOS,=0D + /// with or without overclocking: 0 indicates Not Secured, 1 indicates= Secure.=0D + ///=0D + UINT32 OverclockingSecureStatus : 1;=0D + UINT32 Reserved1 : 29;=0D + UINT32 Reserved2 : 32;=0D + } Bits;=0D + ///=0D + /// All bit fields as a 32-bit value=0D + ///=0D + UINT32 Uint32;=0D + ///=0D + /// All bit fields as a 64-bit value=0D + ///=0D + UINT64 Uint64;=0D +} IA32_OVERCLOCKING_STATUS_REGISTER;=0D +=0D /**=0D Current performance state(P-State) operating point (RO). Introduced at=0D Display Family / Display Model 0F_03H.=0D --=20 2.34.1.windows.1