From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.90164.1673623849597548955 for ; Fri, 13 Jan 2023 07:30:50 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=UBLMa4+m; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673623850; x=1705159850; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=PiyKusCjy1Fc/w4yQPu6oVyesU7sDOIYor/B98JAuLw=; b=UBLMa4+mkvF9GQwxCQyAZQtHnXWLbMGSkL49laxnzp+H7jhmN45uUp5t UTOjAu4tCPTvZoP65Y0DbDcAK+/WwVGgCe93XnyZmdQs5swnHcTwnB23h mSdL+UqXUd2FRXzmDw+DYzwZk7G63W99gKs7+Uq2e+85nqYC7vCae3zm/ LKIcscKOkwSECAinl0i9pljXwgJO2gf53NC3bZOU9BCMIcZk25aY50ShF XurEj2YbQT3j8YjTj2dJjezyhgmz6+vhPTpH1Sgu/fRSKKtuJ90JfhBLK sLBpWjcE39FngZXU0440HULI4Z7Y3uT4+IeHDS+BWqB7dg0AX0jmhsncM g==; X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="410251792" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="410251792" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jan 2023 07:30:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="782182322" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="782182322" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga004.jf.intel.com with ESMTP; 13 Jan 2023 07:30:48 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [PATCH v2 1/4] UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB Data Date: Fri, 13 Jan 2023 23:30:42 +0800 Message-Id: <20230113153045.13060-2-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20230113153045.13060-1-jiaxin.wu@intel.com> References: <20230113153045.13060-1-jiaxin.wu@intel.com> The default SMBASE for the x86 processor is 0x30000. When SMI happens, CPU runs the SMI handler at SMBASE+0x8000. Also, the SMM save state area is within SMBASE+0x10000. One of the SMM initialization from CPU perspective is to program the new SMBASE (in TSEG range) for each CPU thread. When the SMBASE relocated happens in one PEI module ahead of the PiSmmCpuDxeSmm, the PEI module shall produce the SMM_BASE_HOB in HOB database which tells the PiSmmCpuDxeSmm driver which runs at a later phase about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm driver shall install the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Index. When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall program the new SMBASE itself. This patch adds the SMM Base HOB, which can be produced by any PEI module to do the SmBase relocation ahead of PiSmmCpuDxeSmm driver and store the relocated SmBase address in array for reach Processors. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Include/Guid/SmmBaseHob.h | 49 ++++++++++++++++++++++++++++++++++++ UefiCpuPkg/UefiCpuPkg.dec | 3 +++ 2 files changed, 52 insertions(+) create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h b/UefiCpuPkg/Include/Guid/SmmBaseHob.h new file mode 100644 index 0000000000..6ed32481dc --- /dev/null +++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h @@ -0,0 +1,49 @@ +/** @file + The Smm Base HOB is used to store the information of: + * The relocated SmBase in array for each Processors. + + The default SMBASE for the x86 processor is 0x30000. When SMI happens, + CPU runs the SMI handler at SMBASE+0x8000. Also, the SMM save state + area is within SMBASE+0x10000. + + One of the SMM initialization from CPU perspective is to program the + new SMBASE (in TSEG range) for each CPU thread. When the SMBASE update + happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB + in HOB database which tells the PiSmmCpuDxeSmm driver which runs at a + later phase about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm + driver installs the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 + for CPU thread Index. When the HOB doesn't exist, PiSmmCpuDxeSmm driver + shall program the new SMBASE itself. + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_BASE_HOB_H_ +#define SMM_BASE_HOB_H_ + +#include +#include + +#define SMM_BASE_HOB_DATA_GUID \ + { \ + 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73} \ + } + +#pragma pack(1) +typedef struct { + /// + /// Describes the Number of all max supported processors. + /// + UINT64 NumberOfProcessors; + /// + /// Pointer to SmBase address for each Processors. + /// + UINT64 SmBase[]; +} SMM_BASE_HOB_DATA; +#pragma pack() + +extern EFI_GUID gSmmBaseHobGuid; + +#endif diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index cff239d528..2afd08cdd2 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -76,10 +76,13 @@ gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }} ## Include/Guid/MicrocodePatchHob.h gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }} + ## Include/Guid/SmmBaseHob.h + gSmmBaseHobGuid = { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73 }} + [Protocols] ## Include/Protocol/SmmCpuService.h gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }} gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }} -- 2.16.2.windows.1