From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web10.162244.1673859005701758222 for ; Mon, 16 Jan 2023 00:50:05 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=hSpYLEKm; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: william2.wang@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673859005; x=1705395005; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=0WRYrRoHqDqy0eNFX03fhKjzgqfmyyHfW9OUqp1mzg4=; b=hSpYLEKmPD6A3QSV8uPCVVEi73411ZxvnV3NRzISrF8pzlTbEVcXFsZM ryCNL6fPeTWFuxxbdfXX2ELz/IVMYN2cHTTCGA2zg+1Pp36VmKv6Xc94X a5xo2KBHOkcKvRqZOTCuEbcMV9LY3oACNxyT+CpS2N0nJTTMJ3ZEow4Qi R6JqJDssoBB6MK2RLdi4HNdPaAZy3wDUWtbn1EDTpwRXaR4PAr5AINkl0 4wSMtb+6XYwSEejS3GkY+gLFayiERCwAA7cA7mZ4L0A1OE6PV9V1TiWFF 9vbaJcdrqCLcihbVwJ/sn+GZpoXkHCxzdaT4zdcYladEhQHt/EeKjSbfh Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10591"; a="307972544" X-IronPort-AV: E=Sophos;i="5.97,220,1669104000"; d="scan'208";a="307972544" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2023 00:50:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10591"; a="832767487" X-IronPort-AV: E=Sophos;i="5.97,220,1669104000"; d="scan'208";a="832767487" Received: from william4-desk.gar.corp.intel.com ([10.5.215.176]) by orsmga005.jf.intel.com with ESMTP; 16 Jan 2023 00:50:03 -0800 From: william2.wang@intel.com To: devel@edk2.groups.io Cc: William2 Wang , Michael D Kinney , Liming Gao , Ray Ni , Donald Kuo , Chandana C Kumar Subject: [PATCH v4] Update CPUID Leaf 06H to follow latest SDM. Date: Mon, 16 Jan 2023 16:49:59 +0800 Message-Id: <20230116084959.2048-1-william2.wang@intel.com> X-Mailer: git-send-email 2.34.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: William2 Wang REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4262 Update CPUID Leaf 06H to follow latest SDM. Cc: Michael D Kinney Cc: Liming Gao Cc: Ray Ni Cc: Donald Kuo Cc: Chandana C Kumar --- MdePkg/Include/Register/Intel/Cpuid.h | 59 +++++++++++++++++++- 1 file changed, 56 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Registe= r/Intel/Cpuid.h index 350bf60252..9569a8805a 100644 --- a/MdePkg/Include/Register/Intel/Cpuid.h +++ b/MdePkg/Include/Register/Intel/Cpuid.h @@ -1195,12 +1195,24 @@ typedef union { /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supporte= d if set.=0D ///=0D UINT32 FastAccessMode : 1;=0D - UINT32 Reserved4 : 1;=0D + ///=0D + /// [Bit 19] IA32_HW_FEEDBACK_PTR MSR, IA32_HW_FEEDBACK_CONFIG MSR,=0D + /// IA32_PACKAGE_THERM_STATUS MSR bit 26, and IA32_PACKAGE_THERM_INTER= RUPT MSR bit 25 are supported if set.=0D + UINT32 HW_FEEDBACK : 1;=0D ///=0D /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported = if set.=0D ///=0D UINT32 IgnoringIdleLogicalProcessorHWPRequest : 1;=0D - UINT32 Reserved5 : 11;=0D + UINT32 Reserved3 : 2;=0D + ///=0D + /// [Bit 23] Intel Thread Director supported if set. IA32_HW_FEEDBACK_= CHAR and=0D + /// IA32_HW_FEEDBACK_THREAD_CONFIG MSRs are supported if set.=0D + UINT32 ThreadDirector : 1;=0D + ///=0D + /// [Bit 24] IA32_THERM_INTERRUPT MSR bit 25 is supported if set.=0D + ///=0D + UINT32 IA32_THERM_INTERRUPT : 1;=0D + UINT32 Reserved4 : 7;=0D } Bits;=0D ///=0D /// All bit fields as a 32-bit value=0D @@ -1252,7 +1264,13 @@ typedef union { /// (1B0H).=0D ///=0D UINT32 PerformanceEnergyBias : 1;=0D - UINT32 Reserved2 : 28;=0D + UINT32 Reserved2 : 4;=0D + ///=0D + /// {Bit 15:8] Number of Intel Thread Director classes supported by th= e processor. Information for that=0D + /// many classes is written into the Intel Thread Director Table by th= e hardware.=0D + ///=0D + UINT32 ThreadDirectorClasses : 8;=0D + UINT32 Reserved3 : 16;=0D } Bits;=0D ///=0D /// All bit fields as a 32-bit value=0D @@ -1260,6 +1278,41 @@ typedef union { UINT32 Uint32;=0D } CPUID_THERMAL_POWER_MANAGEMENT_ECX;=0D =0D +/**=0D + CPUID Thermal and Power Management Information returned in EDX for CPUID= leaf=0D + #CPUID_THERMAL_POWER_MANAGEMENT.=0D +**/=0D +typedef union {=0D + ///=0D + /// Individual bit fields=0D + ///=0D + struct {=0D + ///=0D + /// {Bits 7:0] Bitmap of supported hardware feedback interface capabil= ities.=0D + /// 0 =3D When set to 1, indicates support for performance capabilit= y reporting.=0D + /// 1 =3D When set to 1, indicates support for energy efficiency cap= ability reporting.=0D + /// 2-7 =3D Reserved=0D + ///=0D + UINT32 InterfaceCapability : 8;=0D + ///=0D + /// {Bits 11:8] Enumerates the size of the hardware feedback interface= structure in number of 4 KB pages;=0D + /// add one to the return value to get the result.=0D + ///=0D + UINT32 InterfaceStructureSize : 4;=0D + UINT32 Reserved : 4;=0D + ///=0D + /// {Bits 31:16] : Index (starting at 0) of this logical processor's r= ow in the hardware feedback interface structure.=0D + /// Note that on some parts the index may be same for multiple logical= processors. On some parts the=0D + /// indices may not be contiguous, i.e., there may be unused rows in t= he hardware feedback interface structure.=0D + ///=0D + UINT32 LogicalProcessorRowIndex : 16;=0D + } Bits;=0D + ///=0D + /// All bit fields as a 32-bit value=0D + ///=0D + UINT32 Uint32;=0D +} CPUID_THERMAL_POWER_MANAGEMENT_EDX;=0D +=0D /**=0D CPUID Structured Extended Feature Flags Enumeration=0D =0D --=20 2.34.1.windows.1