From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mx.groups.io with SMTP id smtpd.web11.42336.1674480805085860876 for ; Mon, 23 Jan 2023 05:33:25 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linux.microsoft.com header.s=default header.b=GWHSjzfX; spf=pass (domain: linux.microsoft.com, ip: 13.77.154.182, mailfrom: eiakovlev@linux.microsoft.com) Received: from localhost.localdomain (unknown [77.64.253.114]) by linux.microsoft.com (Postfix) with ESMTPSA id 2C50520E2C3A for ; Mon, 23 Jan 2023 05:33:24 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 2C50520E2C3A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1674480804; bh=ieXDdsVxPqNpcStLzsW1GQtGY/Ye5ot3kyUQ1WCgpps=; h=From:To:Subject:Date:From; b=GWHSjzfX8AS1AKzdaflKQ1KJubFK2zy6RO9rJe2abvkVj6Aajk3hX7nPWFVR29vvs ZKOEXfKlo0nZwJAQL4jAtxQ1jpjWc3aZKEU2AicnYtLqznTjQhKPEszTWTN5kzGfsI f1qPouMV1nGuTIUYGxE4cv83OrsLJevovAYI/1w8= From: "Evgeny Iakovlev" To: devel@edk2.groups.io Subject: [PATCH] ArmVirtPkg/PrePei: when starting in EL2 configure HCR to not trap on PAC Date: Mon, 23 Jan 2023 14:33:17 +0100 Message-Id: <20230123133317.22491-1-eiakovlev@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable When FEAT_PAuth is impelemented HCR_EL2.APK and HCR_EL2.API bits control whether PAC-related instructions and register accesses should be trapped by the EL2 hypervisor. Note that bit value 0b1 means do NOT trap. When FEAT_PAuth is not implemented or if EL2 is disabled, those bits are ignored and system behaves as if their value was 0b1. When starting in EL2 on ArmVirtPkg get our of the way of a potential hypervisor by setting APK and API bits. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Evgeny Iakovlev --- ArmPkg/Include/Chipset/AArch64.h | 2 ++ ArmPlatformPkg/PrePeiCore/AArch64/Helper.S | 5 +++++ ArmVirtPkg/PrePi/AArch64/ArchPrePi.c | 3 ++- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArc= h64.h index bfd2859f51..da8737236d 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -57,6 +57,8 @@ #define ARM_HCR_AMO BIT5=0D #define ARM_HCR_TSC BIT19=0D #define ARM_HCR_TGE BIT27=0D +#define ARM_HCR_APK BIT40=0D +#define ARM_HCR_API BIT41=0D =0D // Exception Syndrome Register=0D #define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))=0D diff --git a/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S b/ArmPlatformPkg/Pr= ePeiCore/AArch64/Helper.S index 2a604b719b..0f413c5655 100644 --- a/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S +++ b/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S @@ -26,6 +26,11 @@ ASM_FUNC(SetupExceptionLevel2) orr x0, x0, #(1 << 3) // Enable EL2 FIQ=0D orr x0, x0, #(1 << 4) // Enable EL2 IRQ=0D orr x0, x0, #(1 << 5) // Enable EL2 SError and Abort=0D +=0D + // Get out of the way of a poitential EL2 hypervisor by NOT trapping PA= C registers and instructions=0D + orr x0, x0, #(1 << 40) // HCR_EL2.APK=0D + orr x0, x0, #(1 << 41) // HCR_EL2.API=0D +=0D msr hcr_el2, x0 // Write back our settings=0D =0D msr cptr_el2, xzr // Disable copro traps to EL2=0D diff --git a/ArmVirtPkg/PrePi/AArch64/ArchPrePi.c b/ArmVirtPkg/PrePi/AArch6= 4/ArchPrePi.c index 9cab88ca08..29da9d4050 100644 --- a/ArmVirtPkg/PrePi/AArch64/ArchPrePi.c +++ b/ArmVirtPkg/PrePi/AArch64/ArchPrePi.c @@ -22,6 +22,7 @@ ArchInitialize ( =0D if (ArmReadCurrentEL () =3D=3D AARCH64_EL2) {=0D // Trap General Exceptions. All exceptions that would be routed to EL1= are routed to EL2=0D - ArmWriteHcr (ARM_HCR_TGE);=0D + // Also get out of the way of a potential EL2 hypervisor and do NOT tr= ap PAC registers or instructions.=0D + ArmWriteHcr (ARM_HCR_TGE | ARM_HCR_APK | ARM_HCR_API);=0D }=0D }=0D --=20 2.34.1