From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) by mx.groups.io with SMTP id smtpd.web11.1501.1674933495063667873 for ; Sat, 28 Jan 2023 11:18:15 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Wa68aGuO; spf=pass (domain: ventanamicro.com, ip: 209.85.216.47, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f47.google.com with SMTP id e10-20020a17090a630a00b0022bedd66e6dso11802882pjj.1 for ; Sat, 28 Jan 2023 11:18:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Jb8lYvqaZiC3pqnH0QOG28eHJlBLN8LZsm1TK56Th4g=; b=Wa68aGuOjPvDd/ezNAknver3SzN7iYVMaRMPkO3hzY4JRZglRv+d5ugYrIw+Gpn/ht fz4mzTtikwPTT24TRIcyuUoY60wxcjVLT3KCBsLxeEPSTzxbTyvuOYNmokZ3m7xlHkWW T1gBoIJ8mf5x4moguny1NNZvkW0h0f2T0PykWH6GzHipwoowtZW3VTfM6SQ98ijQtrbI p/gdAZzOwKcIXt6Suc4azVyHGebm9mBwueYVg4wnO4G61g7Gl3mShewosVuPstRXc0mh 0Nyjjqlk6/2BAeL7I8ts+rxtNj1JWDBi11d0NurVFFFAxY+ltwS5lLGSODO0Bt1Gfk0B YkuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Jb8lYvqaZiC3pqnH0QOG28eHJlBLN8LZsm1TK56Th4g=; b=HmyGRArn9B5vVUcG1sPf5OoF6gqXhLRrPp7EzLYMcrSbw0DazEdbnV10brtShtuRiq V64fcEhEtz+v/O4ZjwUZr1PXkyKEXrGyotHGXvRkB8S4Ml2eFAx0KEK2KblRnSpX/7XE ANIDNHq3GEJ58TKrO7OImHCmgQqTIKzawpEO/gYZsjgdKZblIZc27MD1y/HQCG26Omjo SCZlrwZ6WVl9gOxP26s0Mowz2MwL+B4CEVLGP4bWmY+TJCtSXp/dSOD0oeBHOBvY0AQm ubKk4vpHGakJG8eZKRXMcFoXaxqc05dJVfvifwgkUQw+AtcSGrNtxjAvDSzw9Xlydn4n A8gA== X-Gm-Message-State: AO0yUKXGigYfHZLq+Sg+qO9D/jKtesPjO+1rj1TaHW4d/MhjKUyuxj97 1QRGdnM9gmYNwDJ/n7vWFadYEh1qNqbamnyV X-Google-Smtp-Source: AK7set8VualNvXrhmWe3Q7r4wCDSD1TqhKh5aTGeefgWK7Xd2naw8Yw+SyC5sXwgKPGLrQameAj9WQ== X-Received: by 2002:a17:903:2282:b0:196:6577:5a8e with SMTP id b2-20020a170903228200b0019665775a8emr4278697plh.39.1674933494218; Sat, 28 Jan 2023 11:18:14 -0800 (PST) Return-Path: Received: from kerodipc.Dlink ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id n9-20020a1709026a8900b00192d9258532sm139923plk.150.2023.01.28.11.18.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Jan 2023 11:18:13 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Abner Chang , Daniel Schaefer , Michael D Kinney , Liming Gao , Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Sami Mujawar , Leif Lindholm , Eric Dong , Ray Ni , Rahul Kumar , Zhiguang Liu , Anup Patel , Heinrich Schuchardt , Andrei Warkentin Subject: [edk2-staging/RiscV64QemuVirt PATCH V7 00/20] Add support for RISC-V virt machine Date: Sun, 29 Jan 2023 00:47:47 +0530 Message-Id: <20230128191807.2080547-1-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.38.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add support for RISC-V qemu virt machine. Most of the changes are migrated from edk2-platforms repo and added qemu specific libraries under OvmfPkg. The series has passed CI tests (https://github.com/tianocore/edk2/pull/3962) The series can be testes as per instructions @ https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support Changes since V6: 1) Took inspiration from IntelTdx and added all RISC-V qemu related libraries and modules in OvmfPkg/RiscVVirt instead of directly under OvmfPkg/Library. Hoping for quicker review since now it shouldn't affect the existing OvmfPkg libraries/modules. 2) Dropped migration of NvVarStoreFormattedLib for now to avoid MdeModulePkg changes. Currently RISC-V Qemu doesn't support separate variable flash. So, it can be taken as a separate activity in future when required. 3) Rebased and new CI test request passed Changes since V5: 1) Avoided editing the existing INF files (as per feedback from Ray Ni). This reduced several refactor patches. 2) Moved to PEI less design (as per suggestion from Andrei Warkentin) 3) Added PciCpuIO2Dxe driver in OvmfPkg. 4) Removed APRIORI requirement in DSC/FDF infrastructure files. Now they are very similar to ArmVirtQemu. 5) Addressed Heinrich's feedback. 6) Rebased and added ack tags Changes since V4: 1) Rebased and added ACKs 2) Dropped few patches related to VirtNorFlashDxe since they are already taken care by Ard. Changes since V3: 1) Addressed Abner's comments 2) Changed folder name from Ia32_X64 to Ia32X64 as per latest guidelines. 2) Rebased Changes since V2: 1) Fixed issues detected by CI 2) Added an extra patch to fix up the consumers of NvVarStoreFormattedLib Changes since V1: 1) Added couple of patches from Ard to optimize the NorFlashDxe in Ovmf. Note: There will be a separate patch series in future to update existing consumers of NorFlashDxe driver. 2) Migrated NvVarStoreFormattedLib from EmbeddedPkg to MdeModulePkg 3) Created Null instance of the NorFlashPlatformLib library class 4) Moved NorFlashPlatformLib.h from ArmPlatformPkg These changes are available at: https://github.com/vlsunil/edk2/tree/RiscV64QemuVirt_v7 Cc: Abner Chang Cc: Daniel Schaefer Cc: Michael D Kinney Cc: Liming Gao Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Sami Mujawar Cc: Leif Lindholm Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Zhiguang Liu Cc: Anup Patel Cc: Heinrich Schuchardt Cc: Andrei Warkentin Sunil V L (20): MdePkg/Register: Add register definition header files for RISC-V MdePkg/BaseLib: RISC-V: Add few more helper functions MdePkg: Add BaseRiscVSbiLib Library for RISC-V UefiCpuPkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions UefiCpuPkg: Add CpuTimerDxe module UefiCpuPkg/CpuExceptionHandlerLib: Add RISC-V instance UefiCpuPkg/CpuDxe: Add RISC-V instance UefiCpuPkg/CpuTimerLib: Add RISC-V instance UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file EmbeddedPkg: Enable PcdPrePiCpuIoSize for RISC-V ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxe OvmfPkg/RiscVVirt: Add PlatformBootManagerLib library OvmfPkg/RiscVVirt: Add PrePiHobListPointerLib library OvmfPkg/RiscVVirt: Add ResetSystemLib library OvmfPkg/RiscVVirt: Add VirtNorFlashPlatformLib library OvmfPkg/RiscVVirt: Add PciCpuIo2Dxe module OvmfPkg/RiscVVirt: Add SEC module OvmfPkg/RiscVVirt: Add build files for Qemu Virt platform Maintainers.txt: Add entry for OvmfPkg/RiscVVirt ArmVirtPkg/ArmVirtPkg.dec | 9 - EmbeddedPkg/EmbeddedPkg.dec | 3 + MdePkg/MdePkg.dec | 4 + OvmfPkg/OvmfPkg.dec | 7 + UefiCpuPkg/UefiCpuPkg.dec | 7 + OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 336 ++++++ ArmVirtPkg/ArmVirtCloudHv.dsc | 2 +- ArmVirtPkg/ArmVirtQemu.dsc | 4 +- ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +- MdePkg/MdePkg.dsc | 3 + ArmVirtPkg/ArmVirtQemu.dsc => OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 276 ++--- UefiCpuPkg/UefiCpuPkg.dsc | 6 + OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 306 ++++++ ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf | 2 +- ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf | 4 +- MdePkg/Library/BaseLib/BaseLib.inf | 3 + MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf | 25 + {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf | 3 +- OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 75 ++ OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf | 23 + OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf | 38 + OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf | 30 + OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 + OvmfPkg/RiscVVirt/Sec/SecMain.inf | 66 ++ UefiCpuPkg/CpuDxe/CpuDxeRiscV64.inf | 68 ++ UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf | 51 + UefiCpuPkg/Library/CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf | 42 + UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf | 32 + MdePkg/Include/Library/BaseLib.h | 50 + MdePkg/Include/Library/BaseRiscVSbiLib.h | 127 +++ MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 119 +++ MdePkg/Include/Register/RiscV64/RiscVImpl.h | 25 + OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.h | 45 + OvmfPkg/RiscVVirt/Sec/SecMain.h | 102 ++ UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 199 ++++ UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h | 177 ++++ UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h | 34 + UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h | 116 +++ MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c | 227 +++++ {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c | 0 OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.c | 1078 ++++++++++++++++++++ OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/QemuKernel.c | 77 ++ OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointer.c | 65 ++ OvmfPkg/RiscVVirt/Library/ResetSystemLib/ResetSystemLib.c | 128 +++ OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c | 40 + OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 557 ++++++++++ OvmfPkg/RiscVVirt/Sec/Cpu.c | 33 + OvmfPkg/RiscVVirt/Sec/Memory.c | 263 +++++ OvmfPkg/RiscVVirt/Sec/Platform.c | 84 ++ OvmfPkg/RiscVVirt/Sec/SecMain.c | 104 ++ UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 365 +++++++ UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.c | 294 ++++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c | 133 +++ UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c | 199 ++++ ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 2 +- Maintainers.txt | 4 + MdePkg/Library/BaseLib/RiscV64/CpuScratch.S | 31 + MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 23 + MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 23 + OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc | 41 + OvmfPkg/RiscVVirt/Sec/SecEntry.S | 21 + OvmfPkg/RiscVVirt/VarStore.fdf.inc | 79 ++ UefiCpuPkg/CpuTimerDxe/CpuTimer.uni | 14 + UefiCpuPkg/CpuTimerDxe/CpuTimerExtra.uni | 12 + UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S | 105 ++ UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 + 67 files changed, 6325 insertions(+), 200 deletions(-) create mode 100644 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc copy ArmVirtPkg/ArmVirtQemu.dsc => OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc (66%) create mode 100644 OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf create mode 100644 MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf rename {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf (89%) create mode 100644 OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf create mode 100644 OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf create mode 100644 OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf create mode 100644 OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf create mode 100644 OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf create mode 100644 OvmfPkg/RiscVVirt/Sec/SecMain.inf create mode 100644 UefiCpuPkg/CpuDxe/CpuDxeRiscV64.inf create mode 100644 UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf create mode 100644 UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf create mode 100644 MdePkg/Include/Library/BaseRiscVSbiLib.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h create mode 100644 OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.h create mode 100644 OvmfPkg/RiscVVirt/Sec/SecMain.h create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h create mode 100644 UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h create mode 100644 UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h create mode 100644 MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c rename {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c (100%) create mode 100644 OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.c create mode 100644 OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/QemuKernel.c create mode 100644 OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointer.c create mode 100644 OvmfPkg/RiscVVirt/Library/ResetSystemLib/ResetSystemLib.c create mode 100644 OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c create mode 100644 OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c create mode 100644 OvmfPkg/RiscVVirt/Sec/Cpu.c create mode 100644 OvmfPkg/RiscVVirt/Sec/Memory.c create mode 100644 OvmfPkg/RiscVVirt/Sec/Platform.c create mode 100644 OvmfPkg/RiscVVirt/Sec/SecMain.c create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c create mode 100644 UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.c create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c create mode 100644 UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuScratch.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S create mode 100644 OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc create mode 100644 OvmfPkg/RiscVVirt/Sec/SecEntry.S create mode 100644 OvmfPkg/RiscVVirt/VarStore.fdf.inc create mode 100644 UefiCpuPkg/CpuTimerDxe/CpuTimer.uni create mode 100644 UefiCpuPkg/CpuTimerDxe/CpuTimerExtra.uni create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S -- 2.38.0