From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) by mx.groups.io with SMTP id smtpd.web10.1515.1674933504366216223 for ; Sat, 28 Jan 2023 11:18:24 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=GPsIusnW; spf=pass (domain: ventanamicro.com, ip: 209.85.214.173, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pl1-f173.google.com with SMTP id m2so2994004plg.4 for ; Sat, 28 Jan 2023 11:18:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=40ldWxVMsf619mIEOsbp0hxUOWPZTW7IDUgkheoFrrc=; b=GPsIusnWVOT33HrbNf0EhxOvSBr12mxBm5SrOCyuWubFMSdYPaIZSppxDGmEWNgcrX FLRLfZDeLmQf3zoplRHhx6lMdqLoIzpui3uAHeHLqMWjfS5mbXfbP5o45MW7/EtbeRRJ 4xnQvDwOWixSbwOUp4AuGdxQSLYNgjJ1OWbaO6p2xcfSOCgfgHRwgp0S0GZuJJr6Cd5C 1IUnzRkdcS+XlLVTjbSmc4CKU5qL4bE1QMU0BDneFwzHSGkQPEE3mAw3owf+cCJwiGIh X4JiMv6Uv7cogf415mwUCKmVFFh0PqWr9N6YxxF0i9nob5Unj/0fB0YSMGLCcDKR/TCi /3dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=40ldWxVMsf619mIEOsbp0hxUOWPZTW7IDUgkheoFrrc=; b=uuTXC9SDac5VnnM0rVuWR/jJMn4zsg6yTCebeaNPJ0ZOhj8YF960hAJstY+V4rj3Sl 8nDVKt1NUDqKCmRExMHKKGSzYXtwyGYPe1XU3q1mTnh1fQ7HhtFaRN2phnhFjDhyhzaz XgfsrwRH1goTE/1VbGNv/zCSvDEWx4sJfqMYalXBuGzreyT5XI54b/9nQIncn35FG2jR 3qcS9Z4qMpPbDUnOQhTFulgduSw2A34gnK2Fwvb/vRY5lI/4ectj910lzmEToMCm4IKQ ulChwZvwCQwXUyA+IjRXb05d3LxOohCqd48a2rqRq5Fr21sgiS8vGzDzc6zObVpXhOVa UTYQ== X-Gm-Message-State: AFqh2kqn1IV6MacZrUuE+EQDbMXzZOK8bUlGT17c6uGoJteWnhGLOpEo 9PKmf7DrT2gYzf5M8WRX3Ve+Wl87NjBwK3VH X-Google-Smtp-Source: AMrXdXvs78eeM6EDCmZmI9BhqxFC6pNnRA1z1Lv+N6YZxMO4jmzVZN3+7U9CRp8v8DC4azBpGhdUPA== X-Received: by 2002:a17:902:9692:b0:189:5f5c:da1d with SMTP id n18-20020a170902969200b001895f5cda1dmr42236599plp.18.1674933503762; Sat, 28 Jan 2023 11:18:23 -0800 (PST) Return-Path: Received: from kerodipc.Dlink ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id n9-20020a1709026a8900b00192d9258532sm139923plk.150.2023.01.28.11.18.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Jan 2023 11:18:23 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Gerd Hoffmann , Abner Chang , Heinrich Schuchardt Subject: [edk2-staging/RiscV64QemuVirt PATCH V7 04/20] UefiCpuPkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions Date: Sun, 29 Jan 2023 00:47:51 +0530 Message-Id: <20230128191807.2080547-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20230128191807.2080547-1-sunilvl@ventanamicro.com> References: <20230128191807.2080547-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add this protocol GUID definition and the header file required. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Heinrich Schuchardt --- UefiCpuPkg/UefiCpuPkg.dec | 7 ++++ UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h | 34 ++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index cff239d5283e..903ad52da91b 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -86,6 +86,13 @@ [Protocols] ## Include/Protocol/SmMonitorInit.h gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }} +[Protocols.RISCV64] + # + # Protocols defined for RISC-V systems + # + ## Include/Protocol/RiscVBootProtocol.h + gRiscVEfiBootProtocolGuid = { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }} + # # [Error.gUefiCpuPkgTokenSpaceGuid] # 0x80000001 | Invalid value provided. diff --git a/UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h b/UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h new file mode 100644 index 000000000000..ed223b852d34 --- /dev/null +++ b/UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h @@ -0,0 +1,34 @@ +/** @file + RISC-V Boot Protocol mandatory for RISC-V UEFI platforms. + + @par Revision Reference: + The protocol specification can be found at + https://github.com/riscv-non-isa/riscv-uefi + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_BOOT_PROTOCOL_H_ +#define RISCV_BOOT_PROTOCOL_H_ + +typedef struct _RISCV_EFI_BOOT_PROTOCOL RISCV_EFI_BOOT_PROTOCOL; + +#define RISCV_EFI_BOOT_PROTOCOL_REVISION 0x00010000 +#define RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION \ + RISCV_EFI_BOOT_PROTOCOL_REVISION + +typedef +EFI_STATUS +(EFIAPI *EFI_GET_BOOT_HARTID)( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ); + +typedef struct _RISCV_EFI_BOOT_PROTOCOL { + UINT64 Revision; + EFI_GET_BOOT_HARTID GetBootHartId; +} RISCV_EFI_BOOT_PROTOCOL; + +#endif -- 2.38.0