From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web10.13635.1674987627529210660 for ; Sun, 29 Jan 2023 02:20:28 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from loongson.cn (unknown [10.2.9.245]) by gateway (Coremail) with SMTP id _____8Ax3epqSNZjv00JAA--.19552S3; Sun, 29 Jan 2023 18:20:26 +0800 (CST) Received: from code-server.gen (unknown [10.2.9.245]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxD79kSNZjyBckAA--.34472S5; Sun, 29 Jan 2023 18:20:25 +0800 (CST) From: "Chao Li" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu Subject: [PATCH v2 3/3] MdePkg: Added serveral tables to MATD used by LoongArch64 Date: Sun, 29 Jan 2023 18:20:17 +0800 Message-Id: <20230129102017.3763122-4-lichao@loongson.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230129102017.3763122-1-lichao@loongson.cn> References: <20230129102017.3763122-1-lichao@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8DxD79kSNZjyBckAA--.34472S5 X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQAGCGPVEG82WgADsp X-Coremail-Antispam: 1Uk129KBjvJXoWxurW5Jr1Duw4DZw4xZF17GFg_yoW5tFWrpr s8uayjqa10qFn7Jw4jqF4agw4fWFsayw18Janaqwn8WF1Ut3ykW3ZxKr4rtFWFyFW0q34j vFWqq347u3WDGrJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bnxFc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4 AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF 7I0E14v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7 CjxVAFwI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2 zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VCjz48v1sIEY20_WwAm72CE4IkC6x 0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64vIr41l42xK82IY6x8ErcxF aVAv8VWrMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxV Cjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY 6xIIjxv20xvE14v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6x AIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY 1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7xRE6wZ7UUUUU== Content-Transfer-Encoding: 8bit Add CORE_PIC, LIO_PIC, HT_PIC, EIO_PIC, MSI_PIC, BIO_PIC and LPC_PIC tables for LoongArch64 as defined in ACPI SPEC 6.5. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4306 Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Chao Li Reviewed-by: Liming Gao --- MdePkg/Include/IndustryStandard/Acpi65.h | 95 +++++++++++++++++++++++- 1 file changed, 94 insertions(+), 1 deletion(-) diff --git a/MdePkg/Include/IndustryStandard/Acpi65.h b/MdePkg/Include/IndustryStandard/Acpi65.h index fdca5316a9..1e41ae9a27 100644 --- a/MdePkg/Include/IndustryStandard/Acpi65.h +++ b/MdePkg/Include/IndustryStandard/Acpi65.h @@ -303,7 +303,7 @@ typedef struct { // // Multiple APIC Description Table APIC structure types -// All other values between 0x10 and 0x7F are reserved and +// All other values between 0x18 and 0x7F are reserved and // will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM. // #define EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC 0x00 @@ -323,6 +323,13 @@ typedef struct { #define EFI_ACPI_6_5_GICR 0x0E #define EFI_ACPI_6_5_GIC_ITS 0x0F #define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP 0x10 +#define EFI_ACPI_6_5_CORE_PIC 0x11 +#define EFI_ACPI_6_5_LIO_PIC 0x12 +#define EFI_ACPI_6_5_HT_PIC 0x13 +#define EFI_ACPI_6_5_EIO_PIC 0x14 +#define EFI_ACPI_6_5_MSI_PIC 0x15 +#define EFI_ACPI_6_5_BIO_PIC 0x16 +#define EFI_ACPI_6_5_LPC_PIC 0x17 // // APIC Structure Definitions @@ -617,6 +624,92 @@ typedef struct { #define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_NOOP 0x0000 #define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_WAKEUP 0x0001 +/// +/// Core Programmable Interrupt Controller +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Version; + UINT32 ProcessorId; + UINT32 CoreId; + UINT32 Flags; +} EFI_ACPI_6_5_CORE_PIC_STRUCTURE; + +/// +/// Legacy I/O Programmable Interrupt Controller +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Version; + UINT64 Address; + UINT16 Size; + UINT8 Cascade[2]; + UINT32 CascadeMap[2]; +} EFI_ACPI_6_5_LIO_PIC_STRUCTURE; + +/// +/// HyperTransport Programmable Interrupt Controller +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Version; + UINT64 Address; + UINT16 Size; + UINT8 Cascade[8]; +} EFI_ACPI_6_5_HT_PIC_STRUCTURE; + +/// +/// Extend I/O Programmable Interrupt Controller +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Version; + UINT8 Cascade; + UINT8 Node; + UINT64 NodeMap; +} EFI_ACPI_6_5_EIO_PIC_STRUCTURE; + +/// +/// MSI Programmable Interrupt Controller +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Version; + UINT64 MsgAddress; + UINT32 Start; + UINT32 Count; +} EFI_ACPI_6_5_MSI_PIC_STRUCTURE; + +/// +/// Bridge I/O Programmable Interrupt Controller +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Version; + UINT64 Address; + UINT16 Size; + UINT16 Id; + UINT16 GsiBase; +} EFI_ACPI_6_5_BIO_PIC_STRUCTURE; + +/// +/// Low Pin Count Programmable Interrupt Controller +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Version; + UINT64 Address; + UINT16 Size; + UINT8 Cascade; +} EFI_ACPI_6_5_LPC_PIC_STRUCTURE; + /// /// Smart Battery Description Table (SBST) /// -- 2.27.0