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From: "Ard Biesheuvel" <ardb@kernel.org>
To: devel@edk2.groups.io
Cc: "Ard Biesheuvel" <ardb@kernel.org>,
	"Michael Kinney" <michael.d.kinney@intel.com>,
	"Liming Gao" <gaoliming@byosoft.com.cn>,
	"Jiewen Yao" <jiewen.yao@intel.com>,
	"Michael Kubacki" <michael.kubacki@microsoft.com>,
	"Sean Brogan" <sean.brogan@microsoft.com>,
	"Rebecca Cran" <quic_rcran@quicinc.com>,
	"Leif Lindholm" <quic_llindhol@quicinc.com>,
	"Sami Mujawar" <sami.mujawar@arm.com>,
	"Taylor Beebe" <t@taylorbeebe.com>,
	"Marvin Häuser" <mhaeuser@posteo.de>
Subject: [RFC PATCH v2 2/7] MdePkg/BasePeCoffLib: Move RISC-V definitions out of generic header
Date: Fri,  3 Feb 2023 13:10:24 +0100	[thread overview]
Message-ID: <20230203121029.2451394-3-ardb@kernel.org> (raw)
In-Reply-To: <20230203121029.2451394-1-ardb@kernel.org>

Generic headers should only contain arch specific definitions if really
needed, which is not the case for the RISC-V based opcode immediate
parsing constants, so move them out of BasePeCoffLibInternals.h.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
 MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h | 9 ---------
 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c   | 9 +++++++++
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
index aa86a54850c6..4a43ec236529 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
@@ -17,15 +17,6 @@
 #include <Library/PeCoffExtraActionLib.h>
 #include <IndustryStandard/PeImage.h>
 
-//
-// Macro definitions for RISC-V architecture.
-//
-#define RV_X(x, s, n)  (((x) >> (s)) & ((1<<(n))-1))
-#define RISCV_IMM_BITS   12
-#define RISCV_IMM_REACH  (1LL<<RISCV_IMM_BITS)
-#define RISCV_CONST_HIGH_PART(VALUE) \
-  (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
-
 /**
   Performs an Itanium-based specific relocation fixup and is a no-op on other
   instruction sets.
diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
index adbfe9ccf580..71daf7fe4554 100644
--- a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
+++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
@@ -7,6 +7,15 @@
 #include "BasePeCoffLibInternals.h"
 #include <Library/BaseLib.h>
 
+//
+// Macro definitions for RISC-V architecture.
+//
+#define RV_X(x, s, n)  (((x) >> (s)) & ((1<<(n))-1))
+#define RISCV_IMM_BITS   12
+#define RISCV_IMM_REACH  (1LL<<RISCV_IMM_BITS)
+#define RISCV_CONST_HIGH_PART(VALUE) \
+  (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
+
 /**
   Performs an RISC-V specific relocation fixup and is a no-op on
   other instruction sets.
-- 
2.39.1


  parent reply	other threads:[~2023-02-03 12:11 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-03 12:10 [RFC PATCH v2 0/7] enable IBT/BTI codegen and reporting to the OS Ard Biesheuvel
2023-02-03 12:10 ` [RFC PATCH v2 1/7] MdePkg: Update MemoryAttributesTable to v2.10 Ard Biesheuvel
2023-02-03 12:10 ` Ard Biesheuvel [this message]
2023-02-03 12:10 ` [RFC PATCH v2 3/7] MdePkg/BasePeCoffLib: Clean up stale Itanium references in comments Ard Biesheuvel
2023-02-03 12:10 ` [RFC PATCH v2 4/7] MdePkg/BasePeCoffLib: Add generic plumbing to detect IBT/BTI support Ard Biesheuvel
2023-02-03 12:10 ` [RFC PATCH v2 5/7] MdePkg/BasePeCoffLib AARCH64: Implement fwd control flow guard detection Ard Biesheuvel
2023-02-03 12:10 ` [RFC PATCH v2 6/7] MdeModulePkg: Enable forward edge CFI in mem attributes table Ard Biesheuvel
2023-02-03 12:10 ` [RFC PATCH v2 7/7] ArmVirtPkg: Implement BTI for runtime regions Ard Biesheuvel
2023-02-03 12:33   ` [edk2-devel] " Michael Brown
2023-02-03 12:55     ` Ard Biesheuvel
2023-02-03 12:58       ` Michael Brown

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