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From: "Ard Biesheuvel" <ardb@kernel.org>
To: devel@edk2.groups.io
Cc: Ard Biesheuvel <ardb@kernel.org>,
	Michael Kinney <michael.d.kinney@intel.com>,
	Liming Gao <gaoliming@byosoft.com.cn>,
	Jiewen Yao <jiewen.yao@intel.com>,
	Michael Kubacki <michael.kubacki@microsoft.com>,
	Sean Brogan <sean.brogan@microsoft.com>,
	Rebecca Cran <quic_rcran@quicinc.com>,
	Leif Lindholm <quic_llindhol@quicinc.com>,
	Sami Mujawar <sami.mujawar@arm.com>,
	Taylor Beebe <t@taylorbeebe.com>,
	=?UTF-8?q?Marvin=20H=C3=A4user?= <mhaeuser@posteo.de>
Subject: [RFC PATCH v2 2/7] MdePkg/BasePeCoffLib: Move RISC-V definitions out of generic header
Date: Fri,  3 Feb 2023 13:10:24 +0100
Message-Id: <20230203121029.2451394-3-ardb@kernel.org>
X-Mailer: git-send-email 2.39.1
In-Reply-To: <20230203121029.2451394-1-ardb@kernel.org>
References: <20230203121029.2451394-1-ardb@kernel.org>
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Generic headers should only contain arch specific definitions if really
needed, which is not the case for the RISC-V based opcode immediate
parsing constants, so move them out of BasePeCoffLibInternals.h.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
 MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h | 9 ---------
 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c   | 9 +++++++++
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h b/MdePkg=
/Library/BasePeCoffLib/BasePeCoffLibInternals.h
index aa86a54850c6..4a43ec236529 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
@@ -17,15 +17,6 @@
 #include <Library/PeCoffExtraActionLib.h>=0D
 #include <IndustryStandard/PeImage.h>=0D
 =0D
-//=0D
-// Macro definitions for RISC-V architecture.=0D
-//=0D
-#define RV_X(x, s, n)  (((x) >> (s)) & ((1<<(n))-1))=0D
-#define RISCV_IMM_BITS   12=0D
-#define RISCV_IMM_REACH  (1LL<<RISCV_IMM_BITS)=0D
-#define RISCV_CONST_HIGH_PART(VALUE) \=0D
-  (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))=0D
-=0D
 /**=0D
   Performs an Itanium-based specific relocation fixup and is a no-op on ot=
her=0D
   instruction sets.=0D
diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/L=
ibrary/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
index adbfe9ccf580..71daf7fe4554 100644
--- a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
+++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
@@ -7,6 +7,15 @@
 #include "BasePeCoffLibInternals.h"=0D
 #include <Library/BaseLib.h>=0D
 =0D
+//=0D
+// Macro definitions for RISC-V architecture.=0D
+//=0D
+#define RV_X(x, s, n)  (((x) >> (s)) & ((1<<(n))-1))=0D
+#define RISCV_IMM_BITS   12=0D
+#define RISCV_IMM_REACH  (1LL<<RISCV_IMM_BITS)=0D
+#define RISCV_CONST_HIGH_PART(VALUE) \=0D
+  (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))=0D
+=0D
 /**=0D
   Performs an RISC-V specific relocation fixup and is a no-op on=0D
   other instruction sets.=0D
--=20
2.39.1