From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web11.7359.1675919657812050493 for ; Wed, 08 Feb 2023 21:14:17 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=jDS7y+uw; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: chasel.chiu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675919657; x=1707455657; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=8175ZpjrzmWqpRBkvvbIxM8D8rge6PPA9OL9f7Ox58s=; b=jDS7y+uwLeZb1ZYmM3aMAm2ZqA1HIFRdG5ty2PZYP2Bo/hIqVT9unEad MzUML0YotlNoc+U1+0KYTLc1rPKEpDZXflBEilPu47+4c+Ji1xS+rTPMH /pWWJkH+SFsdrY50C/KDg/mFuHFEQhCv8e/StBarvq8JlOZVx3oQyAq47 HwngsHAW33K5ZIZmasX3MeNjs8hVRsL9R3v4RmTWVRxDcGvCnpO0lLPaD 2He6BnSzVV7/c7nZLbJIKMw5edFwY0E91vwsuX5lJJ3sMfYbOtNeSt03C KM8UB4xtMQt7hrOh0g7jgNi/MqbFFbiOeRkGzyfPYHio/A0brWP2LaehQ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="357416545" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="357416545" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 21:14:17 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="996401980" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="996401980" Received: from cchiu4-mobl.gar.corp.intel.com ([10.212.221.164]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 21:14:16 -0800 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Ashraf Ali S , Isaac Oram , Rangasai V Chaganty , Ray Ni , Michael Kubacki Subject: [edk2-platforms: PATCH] IntelSiliconPkg/SpiFvbServiceSmm: Support Other NVS variable region. Date: Wed, 8 Feb 2023 21:14:02 -0800 Message-Id: <20230209051402.1319-1-chasel.chiu@intel.com> X-Mailer: git-send-email 2.35.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Platform may implement Other NVS variable region following Regular variable region and in this case SpiFvbService should include both region size when calculating the total NVS region size. One usage model is EventLog NVS region and there could be others. Cc: Ashraf Ali S Cc: Isaac Oram Cc: Rangasai V Chaganty Cc: Ray Ni Cc: Michael Kubacki Signed-off-by: Chasel Chiu --- Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCom= mon.c | 7 +++++++ Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm= .inf | 7 ++++--- Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec = | 8 ++++++++ 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiF= vbServiceCommon.c b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbServi= ce/SpiFvbServiceCommon.c index 942abf95a6..bcde98131d 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServi= ceCommon.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServi= ceCommon.c @@ -568,6 +568,13 @@ GetVariableFvInfo ( return;=0D }=0D =0D + //=0D + // GetVariableFlashNvStorageInfo () only reports regular variable region= information,=0D + // if platform implemented a separate Other variable region following th= e regular variable region,=0D + // the size should be included as overall NVS variable region size.=0D + //=0D + NvStoreLength +=3D PcdGet32 (PcdFlashNvStorageOtherVariableSize);=0D +=0D Status =3D GetVariableFlashFtwSpareInfo (&NvBaseAddress, &Length64);=0D if (!EFI_ERROR (Status)) {=0D // Stay within the current UINT32 size assumptions in the variable sta= ck.=0D diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiF= vbServiceSmm.inf b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbServic= e/SpiFvbServiceSmm.inf index 73049eceb2..f40067418a 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServi= ceSmm.inf +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServi= ceSmm.inf @@ -43,9 +43,10 @@ IntelSiliconPkg/IntelSiliconPkg.dec=0D =0D [Pcd]=0D - gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUM= ES=0D - gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUM= ES=0D - gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ## SOMETI= MES_CONSUMES=0D + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CON= SUMES=0D + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CON= SUMES=0D + gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ## SOM= ETIMES_CONSUMES=0D + gIntelSiliconPkgTokenSpaceGuid.PcdFlashNvStorageOtherVariableSize ## CON= SUMES=0D =0D [Sources]=0D FvbInfo.c=0D diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index 63dae756ad..7034ab93b0 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -194,3 +194,11 @@ # Other value: reserved for future use.
=0D # @Prompt Flash Variable Store type.=0D gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType|0x00|UINT8|0x00= 00000E=0D +=0D + ## Declares Separate NVS Variable Region Size.

=0D + # Platform may implement a Regular variable region and an Other variabl= e region, which will require this PCD=0D + # to tell SpiFvbService to include both regions.
=0D + # 0: No separate Other variable region.
=0D + # non-zero: The size of a separate Other variable region following the = Regular variable region.
=0D + # @Prompt Separate NVS Variable Region Size.=0D + gIntelSiliconPkgTokenSpaceGuid.PcdFlashNvStorageOtherVariableSize|0x0000= 0000|UINT32|0x0000000F=0D --=20 2.35.0.windows.1