From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web11.15542.1675951194221228490 for ; Thu, 09 Feb 2023 05:59:54 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=mFtxeLTt; spf=pass (domain: kernel.org, ip: 139.178.84.217, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B7E1D61AA3; Thu, 9 Feb 2023 13:59:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 016EEC433A0; Thu, 9 Feb 2023 13:59:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1675951193; bh=gG7DrQ/0csDN+fS3jtvOi7eGg9C6dXiB2OM0XD7baHU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mFtxeLTt94QTNEwEJ/iDakxCKwXIfZP4MiTYHRSzApEUvG+3iJCMfdQ3YCNGQq3cu q4o12qHARcpv6O/pw0yzO0p6vWNlpUm/0Fk/GZLf1oDPIHEaD2ixJOfga3P9FI1ByU VmHpDLqI7k2gOxthkIwgdldigSypnbBeDYAOYCCUTeVyVjbTighTx+/Y11EkFqfYR3 pVldoIUTecE947lHcGlSyTySUQGhqiA+cRrw2qlTXmMLzceILJ/CMskNDBTZz0tXbe uUSTwe15MOCDEWarieI9FJ6Q7n8w0mIHWbj+6o5BXSBdF6zdNHakV4ZCtyBOwxauMI sk5m9vBk9lOQw== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Michael Kinney , Liming Gao , Jiewen Yao , Michael Kubacki , Sean Brogan , Rebecca Cran , Leif Lindholm , Sami Mujawar , Taylor Beebe Subject: [PATCH v4 02/11] ArmPkg/ArmMmuLib ARM: Split off XN page descriptor bit from type field Date: Thu, 9 Feb 2023 14:59:27 +0100 Message-Id: <20230209135936.789983-3-ardb@kernel.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230209135936.789983-1-ardb@kernel.org> References: <20230209135936.789983-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable With large page support out of the picture, we can treat bits 1 and 0 of the page descriptor as individual valid and XN bits, instead of treating XN as a page type. Doing so aligns the handling of the attribute with the section descriptor layout, as well as the XN handling on AArch64, and this is beneficial for maintainability. Signed-off-by: Ard Biesheuvel --- ArmPkg/Include/Chipset/ArmV7Mmu.h | 8 +++----- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c | 12 ++++++------ 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/Arm= V7Mmu.h index 7501ebfdf97f..6a2584ceb303 100644 --- a/ArmPkg/Include/Chipset/ArmV7Mmu.h +++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -54,11 +54,9 @@ #define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) = =3D=3D TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)=0D =0D // Translation table descriptor types=0D -#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)=0D -#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)=0D -#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)=0D -#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)=0D -#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)=0D +#define TT_DESCRIPTOR_PAGE_TYPE_MASK (1UL << 1)=0D +#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 1)=0D +#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (1UL << 1)=0D =0D // Section descriptor definitions=0D #define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)=0D diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Librar= y/ArmMmuLib/Arm/ArmMmuLibUpdate.c index 9ca00c976d5f..12d0f4c30f8e 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c @@ -104,12 +104,8 @@ UpdatePageEntries ( =0D // EntryMask: bitmask of values to change (1 =3D change this value, 0 = =3D leave alone)=0D // EntryValue: values at bit positions specified by EntryMask=0D - EntryMask =3D TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK;= =0D - if ((Attributes & EFI_MEMORY_XP) !=3D 0) {=0D - EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN;=0D - } else {=0D - EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE;=0D - }=0D + EntryMask =3D TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK = | TT_DESCRIPTOR_PAGE_XN_MASK;=0D + EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE;=0D =0D // Although the PI spec is unclear on this, the GCD guarantees that only= =0D // one Attribute bit is set at a time, so the order of the conditionals = below=0D @@ -148,6 +144,10 @@ UpdatePageEntries ( EntryValue |=3D TT_DESCRIPTOR_PAGE_AP_RW_RW;=0D }=0D =0D + if ((Attributes & EFI_MEMORY_XP) !=3D 0) {=0D + EntryValue |=3D TT_DESCRIPTOR_PAGE_XN_MASK;=0D + }=0D +=0D // Obtain page table base=0D FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= ();=0D =0D --=20 2.39.1