From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web11.15546.1675951199711367897 for ; Thu, 09 Feb 2023 05:59:59 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=bodTePUY; spf=pass (domain: kernel.org, ip: 139.178.84.217, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1C27161A8D; Thu, 9 Feb 2023 13:59:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 33982C4339B; Thu, 9 Feb 2023 13:59:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1675951198; bh=fJ7vXW33yx4LT56288qKZYnBHS1yszhBWlLQl4RpfAM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bodTePUYcbWq/rqDhqb041+J3tx5kgO2axYib+X2QcXEihW0+mmJ3NfTfjwXyro0n mRNMSWy2J9/3K31sZtAlptom4s44FEVUJvOzwf6KsR69tQ9z41AXoQl6IvoVGfvM9Q wFkXv8fOjo/N1iLBx2G71AI5Xe3qqDEJydxI60biu0ZfSxuI/GNq2H8DC6D0hJz3gJ 9UxzlJYval8qMKzLldLqlbRuCAifa/bYFx9L/gffghhuaIskPn7U0lUtj+Ysm74gYW 0/a+G1Z7/kQ/Hb/JRS6g9cDg4XMDThHMxmEeoWxzJSzDhr67XihREtryoT/cycZyv6 6oioO3dqmwZbg== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Michael Kinney , Liming Gao , Jiewen Yao , Michael Kubacki , Sean Brogan , Rebecca Cran , Leif Lindholm , Sami Mujawar , Taylor Beebe Subject: [PATCH v4 04/11] ArmPkg/ArmMmuLib ARM: Isolate the access flag from AP mask Date: Thu, 9 Feb 2023 14:59:29 +0100 Message-Id: <20230209135936.789983-5-ardb@kernel.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230209135936.789983-1-ardb@kernel.org> References: <20230209135936.789983-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Split the ARM permission fields in the short descriptors into an access flag and AP[2:1] as per the recommendation in the ARM ARM. This makes the access flag available separately, which allows us to implement EFI_MEMORY_RP memory analogous to how it will be implemented for AArch64. Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 47 ++++++++++---------- ArmPkg/Include/Chipset/ArmV7Mmu.h | 40 +++++++++++------ ArmPkg/Library/ArmLib/Arm/ArmV7Support.S | 2 + ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c | 1 + ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c | 12 ++++- 5 files changed, 63 insertions(+), 39 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mm= u.c index 8eb1f71395f5..07faab8216ec 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -50,30 +50,27 @@ SectionToGcdAttributes ( =0D // determine protection attributes=0D switch (SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {=0D - case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write=0D - // *GcdAttributes |=3D EFI_MEMORY_RO | EFI_MEMORY_RP;=0D - break;=0D -=0D - case TT_DESCRIPTOR_SECTION_AP_RW_NO:=0D + case TT_DESCRIPTOR_SECTION_AP_NO_RW:=0D case TT_DESCRIPTOR_SECTION_AP_RW_RW:=0D // normal read/write access, do not add additional attributes=0D break;=0D =0D // read only cases map to write-protect=0D - case TT_DESCRIPTOR_SECTION_AP_RO_NO:=0D + case TT_DESCRIPTOR_SECTION_AP_NO_RO:=0D case TT_DESCRIPTOR_SECTION_AP_RO_RO:=0D *GcdAttributes |=3D EFI_MEMORY_RO;=0D break;=0D -=0D - default:=0D - return EFI_UNSUPPORTED;=0D }=0D =0D // now process eXectue Never attribute=0D - if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) !=3D 0 ) {=0D + if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) !=3D 0) {=0D *GcdAttributes |=3D EFI_MEMORY_XP;=0D }=0D =0D + if ((SectionAttributes & TT_DESCRIPTOR_SECTION_AF) =3D=3D 0) {=0D + *GcdAttributes |=3D EFI_MEMORY_RP;=0D + }=0D +=0D return EFI_SUCCESS;=0D }=0D =0D @@ -114,30 +111,27 @@ PageToGcdAttributes ( =0D // determine protection attributes=0D switch (PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {=0D - case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write=0D - // *GcdAttributes |=3D EFI_MEMORY_RO | EFI_MEMORY_RP;=0D - break;=0D -=0D - case TT_DESCRIPTOR_PAGE_AP_RW_NO:=0D + case TT_DESCRIPTOR_PAGE_AP_NO_RW:=0D case TT_DESCRIPTOR_PAGE_AP_RW_RW:=0D // normal read/write access, do not add additional attributes=0D break;=0D =0D // read only cases map to write-protect=0D - case TT_DESCRIPTOR_PAGE_AP_RO_NO:=0D + case TT_DESCRIPTOR_PAGE_AP_NO_RO:=0D case TT_DESCRIPTOR_PAGE_AP_RO_RO:=0D *GcdAttributes |=3D EFI_MEMORY_RO;=0D break;=0D -=0D - default:=0D - return EFI_UNSUPPORTED;=0D }=0D =0D // now process eXectue Never attribute=0D - if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) !=3D 0 ) {=0D + if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) !=3D 0) {=0D *GcdAttributes |=3D EFI_MEMORY_XP;=0D }=0D =0D + if ((PageAttributes & TT_DESCRIPTOR_PAGE_AF) =3D=3D 0) {=0D + *GcdAttributes |=3D EFI_MEMORY_RP;=0D + }=0D +=0D return EFI_SUCCESS;=0D }=0D =0D @@ -166,6 +160,7 @@ SyncCacheConfigPage ( // Convert SectionAttributes into PageAttributes=0D NextPageAttributes =3D=0D TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (*NextSectionAttributes) |= =0D + TT_DESCRIPTOR_CONVERT_TO_PAGE_AF (*NextSectionAttributes) |=0D TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (*NextSectionAttributes);=0D =0D // obtain page table base=0D @@ -174,7 +169,7 @@ SyncCacheConfigPage ( for (i =3D 0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {=0D if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) =3D=3D TT_DES= CRIPTOR_PAGE_TYPE_PAGE) {=0D // extract attributes (cacheability and permissions)=0D - PageAttributes =3D SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_P= OLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);=0D + PageAttributes =3D SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_P= OLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_AF);=0D =0D if (NextPageAttributes =3D=3D 0) {=0D // start on a new region=0D @@ -213,6 +208,7 @@ SyncCacheConfigPage ( // Convert back PageAttributes into SectionAttributes=0D *NextSectionAttributes =3D=0D TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (NextPageAttributes) |=0D + TT_DESCRIPTOR_CONVERT_TO_SECTION_AF (NextPageAttributes) |=0D TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (NextPageAttributes);=0D =0D return EFI_SUCCESS;=0D @@ -256,14 +252,14 @@ SyncCacheConfig ( FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddres= s ());=0D =0D // Get the first region=0D - NextSectionAttributes =3D FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CA= CHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);=0D + NextSectionAttributes =3D FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CA= CHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | TT_DESCRIPTOR_SECTION_AF)= ;=0D =0D // iterate through each 1MB descriptor=0D NextRegionBase =3D NextRegionLength =3D 0;=0D for (i =3D 0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {=0D if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) =3D=3D TT_D= ESCRIPTOR_SECTION_TYPE_SECTION) {=0D // extract attributes (cacheability and permissions)=0D - SectionAttributes =3D FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CA= CHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);=0D + SectionAttributes =3D FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CA= CHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | TT_DESCRIPTOR_SECTION_AF)= ;=0D =0D if (NextSectionAttributes =3D=3D 0) {=0D // start on a new region=0D @@ -383,6 +379,10 @@ EfiAttributeToArmAttribute ( ArmAttributes |=3D TT_DESCRIPTOR_SECTION_XN_MASK;=0D }=0D =0D + if ((EfiAttributes & EFI_MEMORY_RP) =3D=3D 0) {=0D + ArmAttributes |=3D TT_DESCRIPTOR_SECTION_AF;=0D + }=0D +=0D return ArmAttributes;=0D }=0D =0D @@ -482,6 +482,7 @@ GetMemoryRegion ( *RegionAttributes =3D TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (P= ageAttributes) |=0D TT_DESCRIPTOR_CONVERT_TO_SECTION_S (PageAttributes= ) |=0D TT_DESCRIPTOR_CONVERT_TO_SECTION_XN (PageAttribute= s) |=0D + TT_DESCRIPTOR_CONVERT_TO_SECTION_AF (PageAttribute= s) |=0D TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (PageAttribute= s);=0D }=0D =0D diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/Arm= V7Mmu.h index e0219747df86..da4f3160f8ff 100644 --- a/ArmPkg/Include/Chipset/ArmV7Mmu.h +++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -80,21 +80,21 @@ #define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)=0D #define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)=0D =0D -#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))=0D -#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))=0D -#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))=0D -#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))=0D -#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))=0D -#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))=0D -#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))=0D +#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (1UL << 11))=0D +#define TT_DESCRIPTOR_SECTION_AP_NO_RW ((0UL << 15) | (0UL << 11))=0D +#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (1UL << 11))=0D +#define TT_DESCRIPTOR_SECTION_AP_NO_RO ((1UL << 15) | (0UL << 11))=0D +#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (1UL << 11))=0D =0D -#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))=0D -#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))=0D -#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))=0D -#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))=0D -#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))=0D -#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))=0D -#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))=0D +#define TT_DESCRIPTOR_SECTION_AF (1UL << 10)=0D +=0D +#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (1UL << 5))=0D +#define TT_DESCRIPTOR_PAGE_AP_NO_RW ((0UL << 9) | (0UL << 5))=0D +#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (1UL << 5))=0D +#define TT_DESCRIPTOR_PAGE_AP_NO_RO ((1UL << 9) | (0UL << 5))=0D +#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (1UL << 5))=0D +=0D +#define TT_DESCRIPTOR_PAGE_AF (1UL << 4)=0D =0D #define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)=0D #define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)=0D @@ -124,20 +124,24 @@ #define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)=0D #define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)=0D #define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)=0D +#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AF(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_AF) >> 6) & TT_DESCRIPTOR_PAGE_AF)=0D #define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK)=0D #define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc) ((((Desc) & (0x3= << 12)) >> 6) | (Desc & (0x3 << 2)))=0D =0D #define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & T= T_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)=0D #define TT_DESCRIPTOR_CONVERT_TO_SECTION_S(Desc) ((((Desc) & T= T_DESCRIPTOR_PAGE_S_MASK) << 6) & TT_DESCRIPTOR_SECTION_S_MASK)=0D +#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AF(Desc) ((((Desc) & T= T_DESCRIPTOR_PAGE_AF) << 6) & TT_DESCRIPTOR_SECTION_AF)=0D #define TT_DESCRIPTOR_CONVERT_TO_SECTION_XN(Desc) ((((Desc) & T= T_DESCRIPTOR_PAGE_XN_MASK) << 4) & TT_DESCRIPTOR_SECTION_XN_MASK)=0D #define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc) ((((Desc) & (= 0x3 << 6)) << 6) | (Desc & (0x3 << 2)))=0D =0D #define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MA= SK | TT_DESCRIPTOR_SECTION_NG_MASK | \=0D TT_DESCRIPTOR= _SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \=0D + TT_DESCRIPTOR= _SECTION_AF | \=0D TT_DESCRIPTOR= _SECTION_XN_MASK | TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK)=0D =0D #define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | T= T_DESCRIPTOR_PAGE_S_MASK | \=0D TT_DESCRIPTOR= _PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | \=0D + TT_DESCRIPTOR= _PAGE_AF | \=0D TT_DESCRIPTOR= _PAGE_CACHE_POLICY_MASK)=0D =0D #define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)=0D @@ -159,6 +163,7 @@ TT_DESCRIPTOR_= SECTION_S_SHARED | \=0D TT_DESCRIPTOR_= SECTION_DOMAIN(0) | \=0D TT_DESCRIPTOR_= SECTION_AP_RW_RW | \=0D + TT_DESCRIPTOR_= SECTION_AF | \=0D TT_DESCRIPTOR_= SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)=0D #define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SEC= TION_TYPE_SECTION = | \=0D ((NonSecure) ?= TT_DESCRIPTOR_SECTION_NS : 0) | \=0D @@ -166,6 +171,7 @@ TT_DESCRIPTOR_= SECTION_S_SHARED | \=0D TT_DESCRIPTOR_= SECTION_DOMAIN(0) | \=0D TT_DESCRIPTOR_= SECTION_AP_RW_RW | \=0D + TT_DESCRIPTOR_= SECTION_AF | \=0D TT_DESCRIPTOR_= SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)=0D #define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SEC= TION_TYPE_SECTION = | \=0D ((NonSecure) ?= TT_DESCRIPTOR_SECTION_NS : 0) | \=0D @@ -174,6 +180,7 @@ TT_DESCRIPTOR_= SECTION_DOMAIN(0) | \=0D TT_DESCRIPTOR_= SECTION_AP_RW_RW | \=0D TT_DESCRIPTOR_= SECTION_XN_MASK | \=0D + TT_DESCRIPTOR_= SECTION_AF | \=0D TT_DESCRIPTOR_= SECTION_CACHE_POLICY_SHAREABLE_DEVICE)=0D #define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SEC= TION_TYPE_SECTION = | \=0D ((NonSecure) ? = TT_DESCRIPTOR_SECTION_NS : 0) | \=0D @@ -181,28 +188,33 @@ TT_DESCRIPTOR_S= ECTION_S_NOT_SHARED | \=0D TT_DESCRIPTOR_S= ECTION_DOMAIN(0) | \=0D TT_DESCRIPTOR_S= ECTION_AP_RW_RW | \=0D + TT_DESCRIPTOR_= SECTION_AF | \=0D TT_DESCRIPTOR_S= ECTION_CACHE_POLICY_NON_CACHEABLE)=0D =0D #define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE = | \=0D TT_DESCRIPTOR_PAGE= _NG_GLOBAL | \=0D TT_DESCRIPTOR_PAGE= _S_SHARED | \=0D TT_DESCRIPTOR_PAGE= _AP_RW_RW | \=0D + TT_DESCRIPTOR_PAGE= _AF | \=0D TT_DESCRIPTOR_PAGE= _CACHE_POLICY_WRITE_BACK_ALLOC)=0D #define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE = | \=0D TT_DESCRIPTOR_PAGE= _NG_GLOBAL | \=0D TT_DESCRIPTOR_PAGE= _S_SHARED | \=0D TT_DESCRIPTOR_PAGE= _AP_RW_RW | \=0D + TT_DESCRIPTOR_PAGE= _AF | \=0D TT_DESCRIPTOR_PAGE= _CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)=0D #define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE = | \=0D TT_DESCRIPTOR_PAGE= _NG_GLOBAL | \=0D TT_DESCRIPTOR_PAGE= _S_NOT_SHARED | \=0D TT_DESCRIPTOR_PAGE= _AP_RW_RW | \=0D + TT_DESCRIPTOR_PAGE= _AF | \=0D TT_DESCRIPTOR_PAGE= _XN_MASK | \=0D TT_DESCRIPTOR_PAGE= _CACHE_POLICY_SHAREABLE_DEVICE)=0D #define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE = | \=0D TT_DESCRIPTOR_PAGE= _NG_GLOBAL | \=0D TT_DESCRIPTOR_PAGE= _S_NOT_SHARED | \=0D TT_DESCRIPTOR_PAGE= _AP_RW_RW | \=0D + TT_DESCRIPTOR_PAGE= _AF | \=0D TT_DESCRIPTOR_PAGE= _CACHE_POLICY_NON_CACHEABLE)=0D =0D // First Level Descriptors=0D diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S b/ArmPkg/Library/ArmL= ib/Arm/ArmV7Support.S index 4925f6628e1e..1f396adffc11 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S @@ -16,6 +16,7 @@ .set CTRL_C_BIT, (1 << 2)=0D .set CTRL_B_BIT, (1 << 7)=0D .set CTRL_I_BIT, (1 << 12)=0D +.set CTRL_AFE_BIT,(1 << 29)=0D =0D =0D ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)=0D @@ -64,6 +65,7 @@ ASM_FUNC(ArmInvalidateInstructionCache) ASM_FUNC(ArmEnableMmu)=0D mrc p15,0,R0,c1,c0,0=0D orr R0,R0,#1=0D + orr R0,R0,#CTRL_AFE_BIT=0D mcr p15,0,R0,c1,c0,0=0D dsb=0D isb=0D diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c b/ArmPkg/Libra= ry/ArmMmuLib/Arm/ArmMmuLibConvert.c index 6e2f08a7ce15..52dbfd714029 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c @@ -23,6 +23,7 @@ ConvertSectionAttributesToPageAttributes ( PageAttributes =3D 0;=0D PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionA= ttributes);=0D PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes)= ;=0D + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_AF (SectionAttributes)= ;=0D PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes)= ;=0D PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes)= ;=0D PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes);= =0D diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Librar= y/ArmMmuLib/Arm/ArmMmuLibUpdate.c index 12d0f4c30f8e..484c67476619 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c @@ -104,7 +104,7 @@ UpdatePageEntries ( =0D // EntryMask: bitmask of values to change (1 =3D change this value, 0 = =3D leave alone)=0D // EntryValue: values at bit positions specified by EntryMask=0D - EntryMask =3D TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK = | TT_DESCRIPTOR_PAGE_XN_MASK;=0D + EntryMask =3D TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK = | TT_DESCRIPTOR_PAGE_XN_MASK | TT_DESCRIPTOR_PAGE_AF;=0D EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE;=0D =0D // Although the PI spec is unclear on this, the GCD guarantees that only= =0D @@ -138,6 +138,10 @@ UpdatePageEntries ( return EFI_UNSUPPORTED;=0D }=0D =0D + if ((Attributes & EFI_MEMORY_RP) =3D=3D 0) {=0D + EntryValue |=3D TT_DESCRIPTOR_PAGE_AF;=0D + }=0D +=0D if ((Attributes & EFI_MEMORY_RO) !=3D 0) {=0D EntryValue |=3D TT_DESCRIPTOR_PAGE_AP_RO_RO;=0D } else {=0D @@ -237,7 +241,7 @@ UpdateSectionEntries ( =0D // Make sure we handle a section range that is unmapped=0D EntryMask =3D TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN= _MASK |=0D - TT_DESCRIPTOR_SECTION_AP_MASK;=0D + TT_DESCRIPTOR_SECTION_AP_MASK | TT_DESCRIPTOR_SECTION_AF;=0D EntryValue =3D TT_DESCRIPTOR_SECTION_TYPE_SECTION;=0D =0D // Although the PI spec is unclear on this, the GCD guarantees that only= =0D @@ -281,6 +285,10 @@ UpdateSectionEntries ( EntryValue |=3D TT_DESCRIPTOR_SECTION_XN_MASK;=0D }=0D =0D + if ((Attributes & EFI_MEMORY_RP) =3D=3D 0) {=0D + EntryValue |=3D TT_DESCRIPTOR_SECTION_AF;=0D + }=0D +=0D // obtain page table base=0D FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= ();=0D =0D --=20 2.39.1