From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web11.15548.1675951204128486673 for ; Thu, 09 Feb 2023 06:00:04 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=jkovpwNa; spf=pass (domain: kernel.org, ip: 145.40.68.75, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 7530CB82147; Thu, 9 Feb 2023 14:00:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EFB3EC4339C; Thu, 9 Feb 2023 13:59:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1675951201; bh=gKZ07IyBfxculXsoXWDWTw1WTMwiEIyhUrdvEySYwNs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jkovpwNaVZQiJerW1OOZ6gt6Hxy7D4CtiRQPrs+zNXvn5I0Y2cTrrxF/D6yCoLoo9 IBS9l57GjP+AQqxkyPGyWmp4v+OwcRYYznvbJ+WN3poFDLPzXjatAjKDnookOO1yg6 +VWR6JbvpbrIMg3dkpJM27P4va64BW8Lv5lHE0t2DjAxifW+FH+nq7/Ha8amIDYErc HysRvvF3RFD4bcumUl30OG0smdKDLr6rn6CL+d/RAgoUmYfwVUD3JgEZhHpYQvMkw4 080kcC3Klf0cnUx5sTOnGTMf3NbdI0TRuQk+RcOTcI4LyFvSdK9PGQozCjvWm9RfF6 aaXKlQONyLZag== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Michael Kinney , Liming Gao , Jiewen Yao , Michael Kubacki , Sean Brogan , Rebecca Cran , Leif Lindholm , Sami Mujawar , Taylor Beebe Subject: [PATCH v4 05/11] ArmPkg/ArmMmuLib ARM: Clear individual permission bits Date: Thu, 9 Feb 2023 14:59:30 +0100 Message-Id: <20230209135936.789983-6-ardb@kernel.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230209135936.789983-1-ardb@kernel.org> References: <20230209135936.789983-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Currently, the MMU code that is supposed to clear the RO or XP attributes from a region just clears both unconditionally. This approximates the desired behavior to some extent, but it does mean that setting the RO bit first on a code region, and then clearing the XP bit results both RO and XP being cleared, and we end up with writable code, and avoiding that is the point of all these protections. Once we introduce RP support, this will only get worse, so let's fix this up, by reshuffling the attribute update code to take the entry mask from the caller, and use the mask to preserve other attributes when clearing RO or XP. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c | 94 +++++++++++++++++--- 1 file changed, 81 insertions(+), 13 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Librar= y/ArmMmuLib/Arm/ArmMmuLibUpdate.c index 484c67476619..23f613f5dbb0 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c @@ -81,12 +81,12 @@ UpdatePageEntries ( IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D IN UINT64 Length,=0D IN UINT64 Attributes,=0D + IN UINT32 EntryMask,=0D OUT BOOLEAN *FlushTlbs OPTIONAL=0D )=0D {=0D EFI_STATUS Status;=0D UINT32 EntryValue;=0D - UINT32 EntryMask;=0D UINT32 FirstLevelIdx;=0D UINT32 Offset;=0D UINT32 NumPageEntries;=0D @@ -104,7 +104,6 @@ UpdatePageEntries ( =0D // EntryMask: bitmask of values to change (1 =3D change this value, 0 = =3D leave alone)=0D // EntryValue: values at bit positions specified by EntryMask=0D - EntryMask =3D TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK = | TT_DESCRIPTOR_PAGE_XN_MASK | TT_DESCRIPTOR_PAGE_AF;=0D EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE;=0D =0D // Although the PI spec is unclear on this, the GCD guarantees that only= =0D @@ -220,11 +219,11 @@ EFI_STATUS UpdateSectionEntries (=0D IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D IN UINT64 Length,=0D - IN UINT64 Attributes=0D + IN UINT64 Attributes,=0D + IN UINT32 EntryMask=0D )=0D {=0D EFI_STATUS Status;=0D - UINT32 EntryMask;=0D UINT32 EntryValue;=0D UINT32 FirstLevelIdx;=0D UINT32 NumSections;=0D @@ -240,8 +239,6 @@ UpdateSectionEntries ( // EntryValue: values at bit positions specified by EntryMask=0D =0D // Make sure we handle a section range that is unmapped=0D - EntryMask =3D TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN= _MASK |=0D - TT_DESCRIPTOR_SECTION_AP_MASK | TT_DESCRIPTOR_SECTION_AF;=0D EntryValue =3D TT_DESCRIPTOR_SECTION_TYPE_SECTION;=0D =0D // Although the PI spec is unclear on this, the GCD guarantees that only= =0D @@ -310,6 +307,7 @@ UpdateSectionEntries ( (FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT,= =0D TT_DESCRIPTOR_SECTION_SIZE,=0D Attributes,=0D + ConvertSectionAttributesToPageAttributes (EntryMask),=0D NULL=0D );=0D } else {=0D @@ -340,11 +338,26 @@ UpdateSectionEntries ( return Status;=0D }=0D =0D +/**=0D + Update the permission or memory type attributes on a range of memory.=0D +=0D + @param BaseAddress The start of the region.=0D + @param Length The size of the region.=0D + @param Attributes A mask of EFI_MEMORY_xx constants.=0D + @param SectionMask A mask of short descriptor section attribu= tes=0D + describing which descriptor bits to update= .=0D +=0D + @retval EFI_SUCCESS The attributes were set successfully.=0D + @retval EFI_OUT_OF_RESOURCES The operation failed due to insufficient m= emory.=0D +=0D +**/=0D +STATIC=0D EFI_STATUS=0D -ArmSetMemoryAttributes (=0D +SetMemoryAttributes (=0D IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D IN UINT64 Length,=0D - IN UINT64 Attributes=0D + IN UINT64 Attributes,=0D + IN UINT32 SectionMask=0D )=0D {=0D EFI_STATUS Status;=0D @@ -375,7 +388,12 @@ ArmSetMemoryAttributes ( Attributes=0D ));=0D =0D - Status =3D UpdateSectionEntries (BaseAddress, ChunkLength, Attribute= s);=0D + Status =3D UpdateSectionEntries (=0D + BaseAddress,=0D + ChunkLength,=0D + Attributes,=0D + SectionMask=0D + );=0D =0D FlushTlbs =3D TRUE;=0D } else {=0D @@ -401,6 +419,7 @@ ArmSetMemoryAttributes ( BaseAddress,=0D ChunkLength,=0D Attributes,=0D + ConvertSectionAttributesToPageAttributes (SectionMask),=0D &FlushTlbs=0D );=0D }=0D @@ -420,13 +439,47 @@ ArmSetMemoryAttributes ( return Status;=0D }=0D =0D +/**=0D + Update the permission or memory type attributes on a range of memory.=0D +=0D + @param BaseAddress The start of the region.=0D + @param Length The size of the region.=0D + @param Attributes A mask of EFI_MEMORY_xx constants.=0D +=0D + @retval EFI_SUCCESS The attributes were set successfully.=0D + @retval EFI_OUT_OF_RESOURCES The operation failed due to insufficient m= emory.=0D +=0D +**/=0D +EFI_STATUS=0D +ArmSetMemoryAttributes (=0D + IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D + IN UINT64 Length,=0D + IN UINT64 Attributes=0D + )=0D +{=0D + return SetMemoryAttributes (=0D + BaseAddress,=0D + Length,=0D + Attributes,=0D + TT_DESCRIPTOR_SECTION_TYPE_MASK |=0D + TT_DESCRIPTOR_SECTION_XN_MASK |=0D + TT_DESCRIPTOR_SECTION_AP_MASK |=0D + TT_DESCRIPTOR_SECTION_AF=0D + );=0D +}=0D +=0D EFI_STATUS=0D ArmSetMemoryRegionNoExec (=0D IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D IN UINT64 Length=0D )=0D {=0D - return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP);=0D + return SetMemoryAttributes (=0D + BaseAddress,=0D + Length,=0D + EFI_MEMORY_XP,=0D + TT_DESCRIPTOR_SECTION_XN_MASK=0D + );=0D }=0D =0D EFI_STATUS=0D @@ -435,7 +488,12 @@ ArmClearMemoryRegionNoExec ( IN UINT64 Length=0D )=0D {=0D - return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);=0D + return SetMemoryAttributes (=0D + BaseAddress,=0D + Length,=0D + 0,=0D + TT_DESCRIPTOR_SECTION_XN_MASK=0D + );=0D }=0D =0D EFI_STATUS=0D @@ -444,7 +502,12 @@ ArmSetMemoryRegionReadOnly ( IN UINT64 Length=0D )=0D {=0D - return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);=0D + return SetMemoryAttributes (=0D + BaseAddress,=0D + Length,=0D + EFI_MEMORY_RO,=0D + TT_DESCRIPTOR_SECTION_AP_MASK=0D + );=0D }=0D =0D EFI_STATUS=0D @@ -453,5 +516,10 @@ ArmClearMemoryRegionReadOnly ( IN UINT64 Length=0D )=0D {=0D - return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);=0D + return SetMemoryAttributes (=0D + BaseAddress,=0D + Length,=0D + 0,=0D + TT_DESCRIPTOR_SECTION_AP_MASK=0D + );=0D }=0D --=20 2.39.1