From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) by mx.groups.io with SMTP id smtpd.web10.13397.1676032249481834033 for ; Fri, 10 Feb 2023 04:30:49 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=aiTeqljw; spf=pass (domain: ventanamicro.com, ip: 209.85.216.50, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f50.google.com with SMTP id a8-20020a17090a6d8800b002336b48f653so3576951pjk.3 for ; Fri, 10 Feb 2023 04:30:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=bvpInvYKZcFEMMonQGBGHifVOrUdtI94Cm6Pk3GPCas=; b=aiTeqljwJFnKspqtfi3chKJjQsFflwYyP+TIOOpR1Hh2lYSIFRPpdHovVY0KO5qakF R2CZH2Y8D33pemd1eIdBUtcm1skr+HXTPPVzP7lC0Za+hLBt9gVF2nSu9kz/j/F/0umR +44GZuGkw+e+ZflzbFvPObt+WKdQX+cmZEt8SFpcKAL6aGEeSIvdaxN9THNMls4MFIth niNqOij3A4hI0pp/ytGfCEfSy1qI0pfAc5XQvBYjsYWbC63qTSZXqGWSZXlVFCwbPVub /hmqG1cAxvNcbJcyIycBzfstAgq/ND4zFvj6qWMnV0d32vMC7uT8uiP35Tdjs4I9twYT rPcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=bvpInvYKZcFEMMonQGBGHifVOrUdtI94Cm6Pk3GPCas=; b=6W+pEf0gmqO/btNhsmvhrwNpFEpPz4Z6FSHKbE7PWGHCVWjii+ffaXBUbGqo2hNuiu 84n6oDH4wEOm0t0OjHHYnHwwUEjXHhAe0eT2KL7572vjn1DS/veDhFEoJbG3HkPI0J9Y b9KGG90kUT4EebFTf80nc4LHiDYV9fe6VoKtTRC9JuXz6siS3RuRvaBUDWcxOgEg6CVQ HLuShChBplKzFB7Ke4WS71/C9zPjEYRpP9LSmc/HsdAEOD0K2f9gKBSsIqlTRaKhn3Zm xEsrmbM88RG7p400Jk73aQ8IttHCRyq77zu6wwlIkSXWbM+Cs5lRwFvi7ApVj/cFT7lt Eixg== X-Gm-Message-State: AO0yUKUYiRqKL56IjuIpI5zK3EenwoMG/JSguyprkhAxm5J0C1ZNy9Jj G4Z6YofivoOQxyaVI3MXKs+Xlfzubrd919y6 X-Google-Smtp-Source: AK7set+xwy79RHJGJpOKp+z+3/dYNxoT7Q/g0/Drm4qOfZ7PjlCXov5ksmzhilmxUFuQQEY89R4JNQ== X-Received: by 2002:a17:902:ce85:b0:199:3f98:84f4 with SMTP id f5-20020a170902ce8500b001993f9884f4mr13553513plg.7.1676032248646; Fri, 10 Feb 2023 04:30:48 -0800 (PST) Return-Path: Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:30:48 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Abner Chang , Daniel Schaefer , Michael D Kinney , Liming Gao , Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Sami Mujawar , Leif Lindholm , Eric Dong , Ray Ni , Rahul Kumar , Zhiguang Liu , Anup Patel , Heinrich Schuchardt , Andrei Warkentin Subject: [edk2-staging/RiscV64QemuVirt PATCH V8 00/19] Add support for RISC-V virt machine Date: Fri, 10 Feb 2023 18:00:22 +0530 Message-Id: <20230210123041.1489506-1-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add support for RISC-V qemu virt machine. Most of the changes are migrated from edk2-platforms repo and added qemu specific libraries under OvmfPkg. The series has passed CI tests (https://github.com/tianocore/edk2/pull/4023) These changes are available at: https://github.com/vlsunil/edk2/tree/RiscV64QemuVirt_V8 The series can be tested as per instructions @ https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support Changes since V7: 1) Addressed feedbacks from Mike and Ray. 2) Added Anrdrei as another reviewer for RiscVVirt 3) Rebased 4) Added RB and ACK tags Changes since V6: 1) Took inspiration from IntelTdx and added all RISC-V qemu related libraries and modules in OvmfPkg/RiscVVirt instead of directly under OvmfPkg/Library. Hoping for quicker review since now it shouldn't affect the existing OvmfPkg libraries/modules. 2) Dropped migration of NvVarStoreFormattedLib for now to avoid MdeModulePkg changes. Currently RISC-V Qemu doesn't support separate variable flash. So, it can be taken as a separate activity in future when required. 3) Rebased and new CI test request passed Changes since V5: 1) Avoided editing the existing INF files (as per feedback from Ray Ni). This reduced several refactor patches. 2) Moved to PEI less design (as per suggestion from Andrei Warkentin) 3) Added PciCpuIO2Dxe driver in OvmfPkg. 4) Removed APRIORI requirement in DSC/FDF infrastructure files. Now they are very similar to ArmVirtQemu. 5) Addressed Heinrich's feedback. 6) Rebased and added ack tags Changes since V4: 1) Rebased and added ACKs 2) Dropped few patches related to VirtNorFlashDxe since they are already taken care by Ard. Changes since V3: 1) Addressed Abner's comments 2) Changed folder name from Ia32_X64 to Ia32X64 as per latest guidelines. 2) Rebased Changes since V2: 1) Fixed issues detected by CI 2) Added an extra patch to fix up the consumers of NvVarStoreFormattedLib Changes since V1: 1) Added couple of patches from Ard to optimize the NorFlashDxe in Ovmf. Note: There will be a separate patch series in future to update existing consumers of NorFlashDxe driver. 2) Migrated NvVarStoreFormattedLib from EmbeddedPkg to MdeModulePkg 3) Created Null instance of the NorFlashPlatformLib library class 4) Moved NorFlashPlatformLib.h from ArmPlatformPkg Cc: Abner Chang Cc: Daniel Schaefer Cc: Michael D Kinney Cc: Liming Gao Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Sami Mujawar Cc: Leif Lindholm Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Zhiguang Liu Cc: Anup Patel Cc: Heinrich Schuchardt Cc: Andrei Warkentin Sunil V L (19): MdePkg/Register: Add register definition header files for RISC-V MdePkg/BaseLib: RISC-V: Add few more helper functions MdePkg: Add BaseRiscVSbiLib Library for RISC-V UefiCpuPkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions UefiCpuPkg: Add BaseRiscV64CpuExceptionHandlerLib UefiCpuPkg: Add BaseRiscV64CpuTimerLib library UefiCpuPkg: Add CpuTimerDxeRiscV64 module UefiCpuPkg: Add CpuDxeRiscV64 module UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxe OvmfPkg/RiscVVirt: Add PlatformBootManagerLib library OvmfPkg/RiscVVirt: Add PrePiHobListPointerLib library OvmfPkg/RiscVVirt: Add ResetSystemLib library OvmfPkg/RiscVVirt: Add VirtNorFlashPlatformLib library OvmfPkg/RiscVVirt: Add PciCpuIo2Dxe module OvmfPkg/RiscVVirt: Add SEC module OvmfPkg/RiscVVirt: Add build files for Qemu Virt platform Maintainers.txt: Add entry for OvmfPkg/RiscVVirt ArmVirtPkg/ArmVirtPkg.dec | 9 - MdePkg/MdePkg.dec | 4 + OvmfPkg/OvmfPkg.dec | 7 + UefiCpuPkg/UefiCpuPkg.dec | 7 + OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 336 ++++++ ArmVirtPkg/ArmVirtCloudHv.dsc | 2 +- ArmVirtPkg/ArmVirtQemu.dsc | 4 +- ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +- MdePkg/MdePkg.dsc | 3 + ArmVirtPkg/ArmVirtQemu.dsc => OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 281 ++--- UefiCpuPkg/UefiCpuPkg.dsc | 6 + OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 306 ++++++ ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf | 2 +- ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf | 4 +- MdePkg/Library/BaseLib/BaseLib.inf | 3 + MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf | 26 + {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf | 3 +- OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 75 ++ OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf | 23 + OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf | 38 + OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf | 30 + OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 + OvmfPkg/RiscVVirt/Sec/SecMain.inf | 66 ++ UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 68 ++ UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 51 + UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf | 42 + UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf | 33 + MdePkg/Include/Library/BaseLib.h | 50 + MdePkg/Include/Library/BaseRiscVSbiLib.h | 154 +++ MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 119 +++ MdePkg/Include/Register/RiscV64/RiscVImpl.h | 25 + OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.h | 45 + OvmfPkg/RiscVVirt/Sec/SecMain.h | 102 ++ UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 199 ++++ UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 177 ++++ UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h | 34 + UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLib.h | 116 +++ MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c | 231 +++++ {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c | 0 OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.c | 1078 ++++++++++++++++++++ OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/QemuKernel.c | 77 ++ OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointer.c | 65 ++ OvmfPkg/RiscVVirt/Library/ResetSystemLib/ResetSystemLib.c | 128 +++ OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c | 40 + OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 557 ++++++++++ OvmfPkg/RiscVVirt/Sec/Cpu.c | 33 + OvmfPkg/RiscVVirt/Sec/Memory.c | 263 +++++ OvmfPkg/RiscVVirt/Sec/Platform.c | 84 ++ OvmfPkg/RiscVVirt/Sec/SecMain.c | 104 ++ UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 365 +++++++ UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 294 ++++++ UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLib.c | 133 +++ UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c | 199 ++++ ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 2 +- Maintainers.txt | 5 + MdePkg/Library/BaseLib/RiscV64/CpuScratch.S | 31 + MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 23 + MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 23 + MdePkg/Library/BaseRiscVSbiLib/RiscVSbiEcall.S | 42 + OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc | 41 + OvmfPkg/RiscVVirt/Sec/SecEntry.S | 21 + OvmfPkg/RiscVVirt/VarStore.fdf.inc | 79 ++ UefiCpuPkg/CpuDxeRiscV64/CpuDxe.uni | 13 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeExtra.uni | 14 + UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimer.uni | 14 + UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerExtra.uni | 12 + UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.uni | 13 + UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/SupervisorTrapHandler.S | 105 ++ UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.uni | 14 + UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 + 71 files changed, 6452 insertions(+), 205 deletions(-) create mode 100644 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc copy ArmVirtPkg/ArmVirtQemu.dsc => OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc (66%) create mode 100644 OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf create mode 100644 MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf rename {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf (89%) create mode 100644 OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf create mode 100644 OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf create mode 100644 OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf create mode 100644 OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf create mode 100644 OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf create mode 100644 OvmfPkg/RiscVVirt/Sec/SecMain.inf create mode 100644 UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf create mode 100644 UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf create mode 100644 UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf create mode 100644 UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf create mode 100644 MdePkg/Include/Library/BaseRiscVSbiLib.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h create mode 100644 OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.h create mode 100644 OvmfPkg/RiscVVirt/Sec/SecMain.h create mode 100644 UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h create mode 100644 UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h create mode 100644 UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h create mode 100644 UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLib.h create mode 100644 MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c rename {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c (100%) create mode 100644 OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.c create mode 100644 OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/QemuKernel.c create mode 100644 OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointer.c create mode 100644 OvmfPkg/RiscVVirt/Library/ResetSystemLib/ResetSystemLib.c create mode 100644 OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c create mode 100644 OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c create mode 100644 OvmfPkg/RiscVVirt/Sec/Cpu.c create mode 100644 OvmfPkg/RiscVVirt/Sec/Memory.c create mode 100644 OvmfPkg/RiscVVirt/Sec/Platform.c create mode 100644 OvmfPkg/RiscVVirt/Sec/SecMain.c create mode 100644 UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c create mode 100644 UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c create mode 100644 UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLib.c create mode 100644 UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuScratch.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S create mode 100644 MdePkg/Library/BaseRiscVSbiLib/RiscVSbiEcall.S create mode 100644 OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc create mode 100644 OvmfPkg/RiscVVirt/Sec/SecEntry.S create mode 100644 OvmfPkg/RiscVVirt/VarStore.fdf.inc create mode 100644 UefiCpuPkg/CpuDxeRiscV64/CpuDxe.uni create mode 100644 UefiCpuPkg/CpuDxeRiscV64/CpuDxeExtra.uni create mode 100644 UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimer.uni create mode 100644 UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerExtra.uni create mode 100644 UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.uni create mode 100644 UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/SupervisorTrapHandler.S create mode 100644 UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.uni -- 2.34.1