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From: "Sunil V L" <sunilvl@ventanamicro.com>
To: devel@edk2.groups.io
Cc: Michael D Kinney <michael.d.kinney@intel.com>,
	Liming Gao <gaoliming@byosoft.com.cn>,
	Zhiguang Liu <zhiguang.liu@intel.com>,
	Daniel Schaefer <git@danielschaefer.me>,
	Abner Chang <abner.chang@amd.com>,
	Andrei Warkentin <andrei.warkentin@intel.com>
Subject: [edk2-staging/RiscV64QemuVirt PATCH V8 02/19] MdePkg/BaseLib: RISC-V: Add few more helper functions
Date: Fri, 10 Feb 2023 18:00:24 +0530	[thread overview]
Message-ID: <20230210123041.1489506-3-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Few of the basic helper functions required for any
RISC-V CPU were added in edk2-platforms. To support
qemu virt, they need to be added in BaseLib.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
---
 MdePkg/Library/BaseLib/BaseLib.inf              |  3 ++
 MdePkg/Include/Library/BaseLib.h                | 50 ++++++++++++++++++
 MdePkg/Library/BaseLib/RiscV64/CpuScratch.S     | 31 ++++++++++++
 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S      | 23 +++++++++
 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 ++++++++++++++++++--
 MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S       | 23 +++++++++
 6 files changed, 179 insertions(+), 4 deletions(-)

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 9ed46a584a14..3a48492b1a01 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -401,6 +401,9 @@ [Sources.RISCV64]
   RiscV64/RiscVCpuPause.S           | GCC
   RiscV64/RiscVInterrupt.S          | GCC
   RiscV64/FlushCache.S              | GCC
+  RiscV64/CpuScratch.S              | GCC
+  RiscV64/ReadTimer.S               | GCC
+  RiscV64/RiscVMmu.S                | GCC
 
 [Sources.LOONGARCH64]
   Math64.c
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index f3f59f21c2ea..8f2df76c29a3 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -151,6 +151,56 @@ typedef struct {
 
 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT  8
 
+VOID
+RiscVSetSupervisorScratch (
+  IN UINT64
+  );
+
+UINT64
+RiscVGetSupervisorScratch (
+  VOID
+  );
+
+VOID
+RiscVSetSupervisorStvec (
+  IN UINT64
+  );
+
+UINT64
+RiscVGetSupervisorStvec (
+  VOID
+  );
+
+UINT64
+RiscVGetSupervisorTrapCause (
+  VOID
+  );
+
+VOID
+RiscVSetSupervisorAddressTranslationRegister (
+  IN UINT64
+  );
+
+UINT64
+RiscVReadTimer (
+  VOID
+  );
+
+VOID
+RiscVEnableTimerInterrupt (
+  VOID
+  );
+
+VOID
+RiscVDisableTimerInterrupt (
+  VOID
+  );
+
+VOID
+RiscVClearPendingTimerInterrupt (
+  VOID
+  );
+
 #endif // defined (MDE_CPU_RISCV64)
 
 #if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
new file mode 100644
index 000000000000..5492a500eb5e
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
@@ -0,0 +1,31 @@
+//------------------------------------------------------------------------------
+//
+// CPU scratch register related functions for RISC-V
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+#include <Register/RiscV64/RiscVImpl.h>
+
+.data
+.align 3
+.section .text
+
+//
+// Set Supervisor mode scratch.
+// @param a0 : Value set to Supervisor mode scratch
+//
+ASM_FUNC (RiscVSetSupervisorScratch)
+    csrw CSR_SSCRATCH, a0
+    ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode scratch
+//
+ASM_FUNC (RiscVGetSupervisorScratch)
+    csrr a0, CSR_SSCRATCH
+    ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
new file mode 100644
index 000000000000..39a06efa51ef
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
@@ -0,0 +1,23 @@
+//------------------------------------------------------------------------------
+//
+// Read CPU timer
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+#include <Register/RiscV64/RiscVImpl.h>
+
+.data
+.align 3
+.section .text
+
+//
+// Read TIME CSR.
+// @retval a0 : 64-bit timer.
+//
+ASM_FUNC (RiscVReadTimer)
+    csrr a0, CSR_TIME
+    ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
index 87b3468fc7fd..6a1b90a7e45c 100644
--- a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
@@ -8,13 +8,13 @@
 //
 //------------------------------------------------------------------------------
 
+#include <Register/RiscV64/RiscVImpl.h>
+
 ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)
 ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)
 ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)
 
-#define  SSTATUS_SIE                 0x00000002
-#define  CSR_SSTATUS                 0x100
-  #define  SSTATUS_SPP_BIT_POSITION  8
+#define  SSTATUS_SPP_BIT_POSITION  8
 
 //
 // This routine disables supervisor mode interrupt
@@ -53,11 +53,56 @@ InTrap:
   ret
 
 //
+// Set Supervisor mode trap vector.
+// @param a0 : Value set to Supervisor mode trap vector
+//
+ASM_FUNC (RiscVSetSupervisorStvec)
+    csrrw a1, CSR_STVEC, a0
+    ret
+
+//
+// Get Supervisor mode trap vector.
+// @retval a0 : Value in Supervisor mode trap vector
+//
+ASM_FUNC (RiscVGetSupervisorStvec)
+    csrr a0, CSR_STVEC
+    ret
+
+//
+// Get Supervisor trap cause CSR.
+//
+ASM_FUNC (RiscVGetSupervisorTrapCause)
+    csrrs a0, CSR_SCAUSE, 0
+    ret
+//
 // This routine returns supervisor mode interrupt
 // status.
 //
-ASM_PFX(RiscVGetSupervisorModeInterrupts):
+ASM_FUNC (RiscVGetSupervisorModeInterrupts)
   csrr a0, CSR_SSTATUS
   andi a0, a0, SSTATUS_SIE
   ret
 
+//
+// This routine disables supervisor mode timer interrupt
+//
+ASM_FUNC (RiscVDisableTimerInterrupt)
+    li   a0, SIP_STIP
+    csrc CSR_SIE, a0
+    ret
+
+//
+// This routine enables supervisor mode timer interrupt
+//
+ASM_FUNC (RiscVEnableTimerInterrupt)
+    li    a0, SIP_STIP
+    csrs CSR_SIE, a0
+    ret
+
+//
+// This routine clears pending supervisor mode timer interrupt
+//
+ASM_FUNC (RiscVClearPendingTimerInterrupt)
+    li   a0, SIP_STIP
+    csrc CSR_SIP, a0
+    ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S
new file mode 100644
index 000000000000..ac8f92f38aed
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S
@@ -0,0 +1,23 @@
+//------------------------------------------------------------------------------
+//
+// CPU scratch register related functions for RISC-V
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+#include <Register/RiscV64/RiscVImpl.h>
+
+.data
+.align 3
+.section .text
+
+//
+// Set Supervisor Address Translation and
+// Protection Register.
+//
+ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)
+    csrw  CSR_SATP, a0
+    ret
-- 
2.34.1


  parent reply	other threads:[~2023-02-10 12:30 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-10 12:30 [edk2-staging/RiscV64QemuVirt PATCH V8 00/19] Add support for RISC-V virt machine Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 01/19] MdePkg/Register: Add register definition header files for RISC-V Sunil V L
2023-02-10 12:30 ` Sunil V L [this message]
2023-02-10 18:19   ` [edk2-staging/RiscV64QemuVirt PATCH V8 02/19] MdePkg/BaseLib: RISC-V: Add few more helper functions Michael D Kinney
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 03/19] MdePkg: Add BaseRiscVSbiLib Library for RISC-V Sunil V L
2023-02-10 18:21   ` Michael D Kinney
2023-02-15 23:18     ` Michael D Kinney
2023-02-16  2:12       ` [edk2-devel] " Sunil V L
2023-02-16  3:46       ` Sunil V L
2023-02-16  5:54         ` Michael D Kinney
2023-02-16  6:14           ` Sunil V L
2023-02-16  6:28             ` Andrei Warkentin
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 04/19] UefiCpuPkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 05/19] UefiCpuPkg: Add BaseRiscV64CpuExceptionHandlerLib Sunil V L
2023-02-10 12:54   ` [edk2-devel] " Ni, Ray
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 06/19] UefiCpuPkg: Add BaseRiscV64CpuTimerLib library Sunil V L
2023-02-10 12:46   ` [edk2-devel] " Ni, Ray
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 07/19] UefiCpuPkg: Add CpuTimerDxeRiscV64 module Sunil V L
2023-02-10 12:46   ` Ni, Ray
     [not found]   ` <1742774BE3C3A342.6713@groups.io>
2023-02-10 12:55     ` [edk2-devel] " Ni, Ray
2023-02-10 15:41       ` Sunil V L
2023-02-11 10:03   ` Dhaval Sharma
2023-02-11 12:45     ` Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 08/19] UefiCpuPkg: Add CpuDxeRiscV64 module Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 09/19] UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 10/19] ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 11/19] ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxe Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 12/19] OvmfPkg/RiscVVirt: Add PlatformBootManagerLib library Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 13/19] OvmfPkg/RiscVVirt: Add PrePiHobListPointerLib library Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 14/19] OvmfPkg/RiscVVirt: Add ResetSystemLib library Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 15/19] OvmfPkg/RiscVVirt: Add VirtNorFlashPlatformLib library Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 16/19] OvmfPkg/RiscVVirt: Add PciCpuIo2Dxe module Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 17/19] OvmfPkg/RiscVVirt: Add SEC module Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 18/19] OvmfPkg/RiscVVirt: Add build files for Qemu Virt platform Sunil V L
2023-02-10 12:30 ` [edk2-staging/RiscV64QemuVirt PATCH V8 19/19] Maintainers.txt: Add entry for OvmfPkg/RiscVVirt Sunil V L
2023-02-10 13:20 ` [edk2-staging/RiscV64QemuVirt PATCH V8 00/19] Add support for RISC-V virt machine Yao, Jiewen
2023-02-10 13:49   ` Ard Biesheuvel
2023-02-10 16:22     ` Sunil V L
2023-02-16 22:45 ` [edk2-devel] " dann frazier
2023-02-17  4:27   ` Sunil V L
2023-02-17  9:16     ` Michael Brown
2023-02-17 10:12       ` Heinrich Schuchardt
2023-02-20 17:44     ` Oliver Steffen
2023-02-20 20:00       ` Sunil V L

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