[PATCH v5 3/6] UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB Data

["Wu, Jiaxin" <jiaxin.wu@intel.com>]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337

The default SMBASE for the x86 processor is 0x30000. When
SMI happens, CPU runs the SMI handler at SMBASE+0x8000.
Also, the SMM save state area is within SMBASE+0x10000.

One of the SMM initialization from CPU perspective is to relocate
and program the new SMBASE (in TSEG range) for each CPU thread. When
the SMBASE relocation happens in a PEI module, the PEI module shall
produce the SMM_BASE_HOB in HOB database which tells the
PiSmmCpuDxeSmm driver (runs at a later phase) about the new SMBASE
for each CPU thread. PiSmmCpuDxeSmm driver installs the SMI handler
at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Index. When
the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and
program the new SMBASE itself.

This patch adds the SMM Base HOB for any PEI module to do
the SmBase relocation ahead of PiSmmCpuDxeSmm driver and
store the relocated SmBase address in array for reach
Processors.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zeng Star <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
---
 UefiCpuPkg/Include/Guid/SmmBaseHob.h | 64 ++++++++++++++++++++++++++++++++++++
 UefiCpuPkg/UefiCpuPkg.dec            |  5 ++-
 2 files changed, 68 insertions(+), 1 deletion(-)
 create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h

diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h b/UefiCpuPkg/Include/Guid/SmmBaseHob.h
new file mode 100644
index 0000000000..d22b3b942c
--- /dev/null
+++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h
@@ -0,0 +1,64 @@
+/** @file
+  The Smm Base HOB is used to store the information of:
+  * The relocated SmBase address in array for each Processors.
+
+  The default SMBASE for the x86 processor is 0x30000. When SMI happens, CPU
+  runs the SMI handler at SMBASE+0x8000. Also, the SMM save state area is within
+  SMBASE+0x10000.
+
+  One of the SMM initialization from CPU perspective is to relocate and program
+  the new SMBASE (in TSEG range) for each CPU thread. When the SMBASE relocation
+  happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB
+  database which tells the PiSmmCpuDxeSmm driver (which runs at a later phase)
+  about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm driver installs the
+  SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Index.
+  When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and program
+  the new SMBASE itself.
+
+  Note:
+  SMBASE relocation process needs to program the vender specific hardware
+  interface to set SMBASE, it should be in the thread scope. It's doable to
+  program the hardware interface using DXE MP service protocol in PiSmmCpuDxeSmm
+  entry point. But, considering the standalone MM environment where the CpuMm
+  driver runs in a isolated environment and it cannot invoke any DXE or PEI MP
+  service, we recommend to put the hardware interface programming in a separate
+  PEI module instead of in the PiSmmCpuDxeSmm driver.
+
+  Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SMM_BASE_HOB_H_
+#define SMM_BASE_HOB_H_
+
+#define SMM_BASE_HOB_DATA_GUID \
+  { \
+    0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73}  \
+  }
+
+#pragma pack(1)
+typedef struct {
+  ///
+  /// CpuIndex tells which CPU range this specific HOB instance described.
+  /// If CpuIndex is set to 0, it indicats the HOB describes the CPU from 0 to
+  /// NumberOfCpus - 1. The HOB list may contains multiple this HOB instances.
+  /// Each HOB instances describe the information for CPU from CpuIndex to
+  /// CpuIndex + NumberOfCpus - 1. The instance order in the HOB list is random
+  /// so consumer can not assume the CpuIndex of first instance is 0.
+  ///
+  UINT32    CpuIndex;
+  ///
+  /// Describes the Number of all max supported processors.
+  ///
+  UINT32    NumberOfProcessors;
+  ///
+  /// Pointer to SmBase address for each Processors.
+  ///
+  UINT64    SmBase[1];
+} SMM_BASE_HOB_DATA;
+#pragma pack()
+
+extern EFI_GUID  gSmmBaseHobGuid;
+
+#endif
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index cff239d528..7003a2ba77 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -1,9 +1,9 @@
 ## @file  UefiCpuPkg.dec
 # This Package provides UEFI compatible CPU modules and libraries.
 #
-# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
 
@@ -76,10 +76,13 @@
   gEdkiiCpuFeaturesInitDoneGuid  = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}
 
   ## Include/Guid/MicrocodePatchHob.h
   gEdkiiMicrocodePatchHobGuid    = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}
 
+  ## Include/Guid/SmmBaseHob.h
+  gSmmBaseHobGuid      = { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73 }}
+
 [Protocols]
   ## Include/Protocol/SmmCpuService.h
   gEfiSmmCpuServiceProtocolGuid   = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
   gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }}
 
-- 
2.16.2.windows.1