From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.8363.1676267307290691542 for ; Sun, 12 Feb 2023 21:48:27 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=Nnefc8WM; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676267307; x=1707803307; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=xg3K0ocd0+Vu7Jx/UPi8DODLNcqNd3fcyvGcQZDsN80=; b=Nnefc8WMzuBNKX3tfVqTz6umLcANgmPpoYrC/61YC0mSswiEXQOXQB2D BJxvOLITQRnl794uICATTXlKsmSkR8ZPbHRTfqIsG5PGMyLhrUV6C3z5x HhUjJbuWLgfwpmDZBha7blgMH8kUb6NRZBlTROGpsVxfkOtsm+v6dQ/7d N6DMkd0M0Uh9rmHwn5XeK5uuWacerDvjnMgIF5w45zzfaHqHvjpjqPcqU wSyJRTwdHusnwZ9w6R+t6Phg3/A32/CLtNVVYFVWncBjFkz7IB+b4GSgW VjowQ70tfYf7tJFuxl9DlZ9pVwrSVrHqhvvOzFiEXXF8sgiz38bZIDcBq Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10619"; a="328521109" X-IronPort-AV: E=Sophos;i="5.97,293,1669104000"; d="scan'208";a="328521109" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Feb 2023 21:48:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10619"; a="842649661" X-IronPort-AV: E=Sophos;i="5.97,293,1669104000"; d="scan'208";a="842649661" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga005.jf.intel.com with ESMTP; 12 Feb 2023 21:48:01 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [PATCH v5 3/6] UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB Data Date: Mon, 13 Feb 2023 13:47:48 +0800 Message-Id: <20230213054751.8692-4-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20230213054751.8692-1-jiaxin.wu@intel.com> References: <20230213054751.8692-1-jiaxin.wu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337 The default SMBASE for the x86 processor is 0x30000. When SMI happens, CPU runs the SMI handler at SMBASE+0x8000. Also, the SMM save state area is within SMBASE+0x10000. One of the SMM initialization from CPU perspective is to relocate and program the new SMBASE (in TSEG range) for each CPU thread. When the SMBASE relocation happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB database which tells the PiSmmCpuDxeSmm driver (runs at a later phase) about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm driver installs the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Index. When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and program the new SMBASE itself. This patch adds the SMM Base HOB for any PEI module to do the SmBase relocation ahead of PiSmmCpuDxeSmm driver and store the relocated SmBase address in array for reach Processors. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Include/Guid/SmmBaseHob.h | 64 ++++++++++++++++++++++++++++++++++++ UefiCpuPkg/UefiCpuPkg.dec | 5 ++- 2 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h b/UefiCpuPkg/Include/Guid/SmmBaseHob.h new file mode 100644 index 0000000000..d22b3b942c --- /dev/null +++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h @@ -0,0 +1,64 @@ +/** @file + The Smm Base HOB is used to store the information of: + * The relocated SmBase address in array for each Processors. + + The default SMBASE for the x86 processor is 0x30000. When SMI happens, CPU + runs the SMI handler at SMBASE+0x8000. Also, the SMM save state area is within + SMBASE+0x10000. + + One of the SMM initialization from CPU perspective is to relocate and program + the new SMBASE (in TSEG range) for each CPU thread. When the SMBASE relocation + happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB + database which tells the PiSmmCpuDxeSmm driver (which runs at a later phase) + about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm driver installs the + SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Index. + When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and program + the new SMBASE itself. + + Note: + SMBASE relocation process needs to program the vender specific hardware + interface to set SMBASE, it should be in the thread scope. It's doable to + program the hardware interface using DXE MP service protocol in PiSmmCpuDxeSmm + entry point. But, considering the standalone MM environment where the CpuMm + driver runs in a isolated environment and it cannot invoke any DXE or PEI MP + service, we recommend to put the hardware interface programming in a separate + PEI module instead of in the PiSmmCpuDxeSmm driver. + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_BASE_HOB_H_ +#define SMM_BASE_HOB_H_ + +#define SMM_BASE_HOB_DATA_GUID \ + { \ + 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73} \ + } + +#pragma pack(1) +typedef struct { + /// + /// CpuIndex tells which CPU range this specific HOB instance described. + /// If CpuIndex is set to 0, it indicats the HOB describes the CPU from 0 to + /// NumberOfCpus - 1. The HOB list may contains multiple this HOB instances. + /// Each HOB instances describe the information for CPU from CpuIndex to + /// CpuIndex + NumberOfCpus - 1. The instance order in the HOB list is random + /// so consumer can not assume the CpuIndex of first instance is 0. + /// + UINT32 CpuIndex; + /// + /// Describes the Number of all max supported processors. + /// + UINT32 NumberOfProcessors; + /// + /// Pointer to SmBase address for each Processors. + /// + UINT64 SmBase[1]; +} SMM_BASE_HOB_DATA; +#pragma pack() + +extern EFI_GUID gSmmBaseHobGuid; + +#endif diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index cff239d528..7003a2ba77 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -1,9 +1,9 @@ ## @file UefiCpuPkg.dec # This Package provides UEFI compatible CPU modules and libraries. # -# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -76,10 +76,13 @@ gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }} ## Include/Guid/MicrocodePatchHob.h gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }} + ## Include/Guid/SmmBaseHob.h + gSmmBaseHobGuid = { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73 }} + [Protocols] ## Include/Protocol/SmmCpuService.h gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }} gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }} -- 2.16.2.windows.1