From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.groups.io with SMTP id smtpd.web11.14040.1676294188246901241 for ; Mon, 13 Feb 2023 05:16:28 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=dNx8AYK8; spf=pass (domain: redhat.com, ip: 170.10.129.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1676294187; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=rsz2V7K5Arqc3ckQVvCppUYMIRaqQuCynkP/SBKtPUc=; b=dNx8AYK8/22mJ2ynG4cxnWFASzjxtp9LiwpTOYLcRYzoXXM2084m0tGHssJlY7cdrhfU4E N0u2FLh9iDx0ivhRtZYCUBJq1SEhhHrplXx/13rNgOcaQpiQIaxwlVH0iHVKjrh365qkX5 NRZAoDLWp1BjFZBcVi+i+cABW/IbTyM= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-399-uZ2KiIYuOpeP4_68zVRTCQ-1; Mon, 13 Feb 2023 08:16:22 -0500 X-MC-Unique: uZ2KiIYuOpeP4_68zVRTCQ-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id B3375100F901; Mon, 13 Feb 2023 13:16:21 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.45]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 70DBC2166B26; Mon, 13 Feb 2023 13:16:21 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 05E371800082; Mon, 13 Feb 2023 14:16:14 +0100 (CET) Date: Mon, 13 Feb 2023 14:16:14 +0100 From: "Gerd Hoffmann" To: Jiaxin Wu Cc: devel@edk2.groups.io, Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Rahul Kumar Subject: Re: [PATCH v6 4/6] UefiCpuPkg/PiSmmCpuDxeSmm: Consume SMM Base Hob for SmBase info Message-ID: <20230213131614.3vw4q233wtkqkpmv@sirius.home.kraxel.org> References: <20230213084417.9232-1-jiaxin.wu@intel.com> <20230213084417.9232-5-jiaxin.wu@intel.com> MIME-Version: 1.0 In-Reply-To: <20230213084417.9232-5-jiaxin.wu@intel.com> X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi, > + if (GuidHob != NULL) { > + // > + // Check whether the Required TileSize is enough. > + // > + if (TileSize > SIZE_8KB) { > + DEBUG ((DEBUG_ERROR, "The Range of Smbase in SMRAM is not enough -- Required TileSize = 0x%08x, Actual TileSize = 0x%08x\n", TileSize, SIZE_8KB)); > + CpuDeadLoop (); > + return RETURN_BUFFER_TOO_SMALL; > + } Ok, so TileSize is what the firmware needs to store code and state. Where does the SIZE_8KB come from? I assume this is the amount of per-cpu memory allocated by the PEI module? Shouldn't this be passed in the HOB instead of being hard-coded? > + // Allocate buffer for all of the tiles. > + // > + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual > + // Volume 3C, Section 34.11 SMBASE Relocation > + // For Pentium and Intel486 processors, the SMBASE values must be > + // aligned on a 32-KByte boundary or the processor will enter shutdown > + // state during the execution of a RSM instruction. > + // > + // Intel486 processors: FamilyId is 4 > + // Pentium processors : FamilyId is 5 > + // > + BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1)); I think correct is: BufferPages = EFI_SIZE_TO_PAGES(TileSize * mMaxNumberOfCpus); > + if ((FamilyId == 4) || (FamilyId == 5)) { > + Buffer = AllocateAlignedCodePages (BufferPages, SIZE_32KB); Does that actually matter still? I'm pretty sure we can safely use "ASSERT(FamilyId > 5)" here. Pentium processors have been built in the last century, predating x64. Beside that the code is broken for SMP, only cpu0 will get a properly aligned smbase. Not sure penium processors support SMP in the first place though ... > for (Index = 0; Index < mMaxNumberOfCpus; Index++) { > - mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET; > + mCpuHotPlugData.SmBase[Index] = mSmmRelocated ? (UINTN)SmmBaseHobData->SmBase[Index] : (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET; For Index = 0 this evaluates to "Buffer - SMM_HANDLER_OFFSET", which looks wrong to me. take care, Gerd