From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.groups.io with SMTP id smtpd.web11.3311.1676369985868004959 for ; Tue, 14 Feb 2023 02:19:46 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=fiPM86O5; spf=pass (domain: redhat.com, ip: 170.10.129.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1676369985; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Rzihxk+kiJlR7ZggiMpQDu8HRld7KZ8OhE8cMtlsXAQ=; b=fiPM86O54dk8X1T7bPLM890GLRFL8o2JJfcepMqmoNspTr97rPnOPuqtwNxSsKXRfYhg7c bV98Z0krTd9b4gQukVPOeL+rIgTILgfpUFQRXk1TplJ+Yk2BBJ+wJT2jRbaZ9jOTXMMT6Q AT3b45o6DFRm00iuaLbzcg/6YSjWdNY= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-605-JTLhUAvTM1uBHr5bcw7mUw-1; Tue, 14 Feb 2023 05:19:41 -0500 X-MC-Unique: JTLhUAvTM1uBHr5bcw7mUw-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 472D3971090; Tue, 14 Feb 2023 10:19:41 +0000 (UTC) Received: from sirius.home.kraxel.org (ovpn-195-41.brq.redhat.com [10.40.195.41]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1495A2026D4B; Tue, 14 Feb 2023 10:19:41 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id A8DB61802381; Tue, 14 Feb 2023 11:19:39 +0100 (CET) Date: Tue, 14 Feb 2023 11:19:39 +0100 From: "Gerd Hoffmann" To: Jiaxin Wu Cc: devel@edk2.groups.io, Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Rahul Kumar Subject: Re: [PATCH v7 3/6] UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB Data Message-ID: <20230214101939.io45xksnuaxqvjmt@sirius.home.kraxel.org> References: <20230214083314.15092-1-jiaxin.wu@intel.com> <20230214083314.15092-4-jiaxin.wu@intel.com> MIME-Version: 1.0 In-Reply-To: <20230214083314.15092-4-jiaxin.wu@intel.com> X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Feb 14, 2023 at 04:33:11PM +0800, Jiaxin Wu wrote: > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337 > > The default SMBASE for the x86 processor is 0x30000. When > SMI happens, CPU runs the SMI handler at SMBASE+0x8000. > Also, the SMM save state area is within SMBASE+0x10000. > > One of the SMM initialization from CPU perspective is to relocate > and program the new SMBASE (in TSEG range) for each CPU thread. When > the SMBASE relocation happens in a PEI module, the PEI module shall > produce the SMM_BASE_HOB in HOB database which tells the > PiSmmCpuDxeSmm driver (runs at a later phase) about the new SMBASE > for each CPU thread. PiSmmCpuDxeSmm driver installs the SMI handler > at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Index. When > the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and > program the new SMBASE itself. > > This patch adds the SMM Base HOB for any PEI module to do > the SmBase relocation ahead of PiSmmCpuDxeSmm driver and > store the relocated SmBase address in array for reach > Processors. > > Cc: Eric Dong > Cc: Ray Ni > Cc: Zeng Star > Cc: Laszlo Ersek > Cc: Gerd Hoffmann > Cc: Rahul Kumar > Signed-off-by: Jiaxin Wu > --- > UefiCpuPkg/Include/Guid/SmmBaseHob.h | 64 ++++++++++++++++++++++++++++++++++++ > UefiCpuPkg/UefiCpuPkg.dec | 5 ++- > 2 files changed, 68 insertions(+), 1 deletion(-) > create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h > > diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h b/UefiCpuPkg/Include/Guid/SmmBaseHob.h > new file mode 100644 > index 0000000000..4aae0d23ff > --- /dev/null > +++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h > @@ -0,0 +1,64 @@ > +/** @file > + The Smm Base HOB is used to store the information of: > + * The relocated SmBase address in array for each Processors. > + > + The default SMBASE for the x86 processor is 0x30000. When SMI happens, CPU > + runs the SMI handler at SMBASE+0x8000. Also, the SMM save state area is within > + SMBASE+0x10000. > + > + One of the SMM initialization from CPU perspective is to relocate and program > + the new SMBASE (in TSEG range) for each CPU thread. When the SMBASE relocation > + happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB > + database which tells the PiSmmCpuDxeSmm driver (which runs at a later phase) > + about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm driver installs the > + SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Index. > + When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and program > + the new SMBASE itself. This should also explain the consequences of the tiling allocation, i.e. each cpu has one page at SMBASE+0x8000 for the SMI handler and one page at SMBASE+0xF000 for the CPU state. take care, Gerd