From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.1668.1676515600234036658 for ; Wed, 15 Feb 2023 18:46:44 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=U60j9/m+; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676515604; x=1708051604; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=zRrhMNO5KhIq27fQGEBSEMuJr9wBGPl8czGlCqojbS8=; b=U60j9/m+dctClAyolwubNPoMtbiKTuFdcbXcWjyYKchjpWoY3ZrpDorZ QQTtG47DwvB50/Wmvg+zl1GW7SwL6xnex0bI9HzY9AG7OLq0yoqykyt2B VZOk4anWcQlYiPorKwseUZBczSXs9DmBqYoHBjnzcDTT0nB8Ys+8wZcHB 8MBf56DD/6MaZvXV6AtVyS3EdlgSAu3cZAAcJ9Q4lSblrWc4syRxxNXpH 0J+FMJ0EOT0O6oVDi7DyT24Rcba+Vn8699GdwRvLxAdUjxi5zImMfmEA2 sMxsdS+pHrrQYlA3xQbWC4N9GTa/lACKWPV79QJ/UOm6CmxoliRAMox+q g==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="329331587" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329331587" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 18:46:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="758759769" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="758759769" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by FMSMGA003.fm.intel.com with ESMTP; 15 Feb 2023 18:46:41 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [PATCH v8 2/6] UefiCpuPkg/PiSmmCpuDxeSmm: Replace mIsBsp by mBspApicId check Date: Thu, 16 Feb 2023 10:46:31 +0800 Message-Id: <20230216024635.9316-3-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20230216024635.9316-1-jiaxin.wu@intel.com> References: <20230216024635.9316-1-jiaxin.wu@intel.com> This patch is to replace mIsBsp by mBspApicId check. mIsBsp becomes the local variable (IsBsp), then it can be checked dynamically in the function. Instead, we define the mBspApicId, which is to record the BSP ApicId used for compare in SmmInitHandler. With this change, SmmInitHandler can be run in parallel during SMM init. Note: This patch is the per-prepared work by refining the SmmInitHandler, then, we can do the next step to combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one (gcSmiHandlerTemplate), the new SMI handler will call the SmmInitHandler in parallel to do the init. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu Reviewed-by: Ray Ni Reviewed-by: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c index 2ac655d032..6e795d1756 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -57,11 +57,10 @@ SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate = &mSmmCpuPrivateData; // // SMM Relocation variables // volatile BOOLEAN *mRebased; -volatile BOOLEAN mIsBsp; /// /// Handle for the SMM CPU Protocol /// EFI_HANDLE mSmmCpuHandle = NULL; @@ -83,10 +82,12 @@ EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = { EdkiiSmmClearMemoryAttributes }; EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER]; +UINT32 mBspApicId = 0; + // // SMM stack information // UINTN mSmmStackArrayBase; UINTN mSmmStackArrayEnd; @@ -341,39 +342,42 @@ VOID EFIAPI SmmInitHandler ( VOID ) { - UINT32 ApicId; - UINTN Index; + UINT32 ApicId; + UINTN Index; + BOOLEAN IsBsp; // // Update SMM IDT entries' code segment and load IDT // AsmWriteIdtr (&gcSmiIdtr); ApicId = GetApicId (); + IsBsp = (BOOLEAN)(mBspApicId == ApicId); + ASSERT (mNumberOfCpus <= mMaxNumberOfCpus); for (Index = 0; Index < mNumberOfCpus; Index++) { if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) { // // Initialize SMM specific features on the currently executing CPU // SmmCpuFeaturesInitializeProcessor ( Index, - mIsBsp, + IsBsp, gSmmCpuPrivate->ProcessorInfo, &mCpuHotPlugData ); if (!mSmmS3Flag) { // // Check XD and BTS features on each processor on normal boot // CheckFeatureSupported (); - } else if (mIsBsp) { + } else if (IsBsp) { // // BSP rebase is already done above. // Initialize private data during S3 resume // InitializeMpSyncData (); @@ -405,11 +409,10 @@ SmmRelocateBases ( { UINT8 BakBuf[BACK_BUF_SIZE]; SMRAM_SAVE_STATE_MAP BakBuf2; SMRAM_SAVE_STATE_MAP *CpuStatePtr; UINT8 *U8Ptr; - UINT32 ApicId; UINTN Index; UINTN BspIndex; // // Make sure the reserved size is large enough for procedure SmmInitTemplate. @@ -446,21 +449,20 @@ SmmRelocateBases ( CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize); // // Retrieve the local APIC ID of current processor // - ApicId = GetApicId (); + mBspApicId = GetApicId (); // // Relocate SM bases for all APs // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate // - mIsBsp = FALSE; BspIndex = (UINTN)-1; for (Index = 0; Index < mNumberOfCpus; Index++) { mRebased[Index] = FALSE; - if (ApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) { + if (mBspApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) { SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId); // // Wait for this AP to finish its 1st SMI // while (!mRebased[Index]) { @@ -475,12 +477,11 @@ SmmRelocateBases ( // // Relocate BSP's SMM base // ASSERT (BspIndex != (UINTN)-1); - mIsBsp = TRUE; - SendSmiIpi (ApicId); + SendSmiIpi (mBspApicId); // // Wait for the BSP to finish its 1st SMI // while (!mRebased[BspIndex]) { } -- 2.16.2.windows.1