From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.1668.1676515600234036658 for ; Wed, 15 Feb 2023 18:46:45 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=cwpeXrWs; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676515605; x=1708051605; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=1njqzvU5j2PxEKXCsHgYLrfpgPxScXSNEierYJOngW0=; b=cwpeXrWsEJfcXLlyLRBkqK+JEv0k2GkxHOFYdhrkZz3GdiT9DBoi15wi cAee/Kpycg3xZlWfe9l80qHgs3WmHDczsqjZ535kw0KFe/tpUQuoiwXoK hBW3Hd4j1Z+N5QZndlOAf816hnzuSPRKWxrOKV7h2I2cwe7znUGXf3Fo2 m5o4NY0JUvoWnD4tWf69Xe5BMj/Zmaxzps4bIe1iqBpMzkhfXbh4LXy4E 8Ao2fTe2KA57PHhdkPRKN/SzHQpGDi/yAwGsfn7QiXvvuST2MxnHGbubE pCYhDRYCUE5oaBxrVan7j2/YOaHFji4+Wq20XC0JKq4VWsLBPjZXoqsp+ w==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="329331609" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329331609" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 18:46:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="758759775" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="758759775" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by FMSMGA003.fm.intel.com with ESMTP; 15 Feb 2023 18:46:43 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [PATCH v8 3/6] UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB Data Date: Thu, 16 Feb 2023 10:46:32 +0800 Message-Id: <20230216024635.9316-4-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20230216024635.9316-1-jiaxin.wu@intel.com> References: <20230216024635.9316-1-jiaxin.wu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337 The default SMBASE for the x86 processor is 0x30000. When SMI happens, CPU runs the SMI handler at SMBASE+0x8000. Also, the SMM save state area is within SMBASE+0x10000. One of the SMM initialization from CPU perspective is to relocate and program the new SMBASE (in TSEG range) for each CPU thread. When the SMBASE relocation happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB database which tells the PiSmmCpuDxeSmm driver (runs at a later phase) about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm driver installs the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Index. When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and program the new SMBASE itself. This patch adds the SMM Base HOB for any PEI module to do the SmBase relocation ahead of PiSmmCpuDxeSmm driver and store the relocated SmBase address in array for reach Processors. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Include/Guid/SmmBaseHob.h | 75 ++++++++++++++++++++++++++++++++++++ UefiCpuPkg/UefiCpuPkg.dec | 5 ++- 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h b/UefiCpuPkg/Include/Guid/SmmBaseHob.h new file mode 100644 index 0000000000..9434276991 --- /dev/null +++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h @@ -0,0 +1,75 @@ +/** @file + The Smm Base HOB is used to store the information of: + * The relocated SmBase address in array for each Processors. + + The default Smbase for the x86 processor is 0x30000. When SMI happens, CPU + runs the SMI handler at Smbase+0x8000. Also, the SMM save state area is within + Smbase+0x10000. Since it's the start address to store the CPU save state and + code for the SMI entry point, those info are tiled within an SMRAM allocated + or reserved buffer. This tile size shall be enough to cover 3 parts: + 1. CPU SMRAM Save State Map starts at Smbase + 0xfc00 + 2. Extra CPU specific context start starts at Smbase + 0xfb00 + 3. SMI entry point starts at Smbase + 0x8000. + Besides, This size should be rounded up to nearest power of 2. The Smm Base HOB + producer should be responsible for reserving enough size. + + One of the SMM initialization from CPU perspective is to relocate and program + the new Smbase (in TSEG range) for each CPU thread. When the Smbase relocation + happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB + database which tells the PiSmmCpuDxeSmm driver (which runs at a later phase) + about the new Smbase for each CPU thread. PiSmmCpuDxeSmm driver installs the + SMI handler at the SMM_BASE_HOB.Smbase[Index]+0x8000 for CPU thread Index. + When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and program + the new Smbase itself. + + Note: + 1. Smbase relocation process needs to program the vender specific hardware + interface to set Smbase, it should be in the thread scope. It's doable to + program the hardware interface using DXE MP service protocol in PiSmmCpuDxeSmm + entry point. But, considering the standalone MM environment where the CpuMm + driver runs in a isolated environment and it cannot invoke any DXE or PEI MP + service, we recommend to put the hardware interface programming in a separate + PEI module instead of in the PiSmmCpuDxeSmm driver. + + 2. There is the hard requirement that SMI Entry Size <= 0x1000, data Size <= + 0x1000 in PiSmmCpuDxeSmm. So, this require the allocated or reserved buffer in + SMRAM should be >= 0x2000. + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_BASE_HOB_H_ +#define SMM_BASE_HOB_H_ + +#define SMM_BASE_HOB_DATA_GUID \ + { \ + 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73} \ + } + +#pragma pack(1) +typedef struct { + /// + /// CpuIndex tells which CPU range this specific HOB instance described. + /// If CpuIndex is set to 0, it indicats the HOB describes the CPU from 0 to + /// NumberOfCpus - 1. The HOB list may contains multiple this HOB instances. + /// Each HOB instances describe the information for CPU from CpuIndex to + /// CpuIndex + NumberOfCpus - 1. The instance order in the HOB list is random + /// so consumer can not assume the CpuIndex of first instance is 0. + /// + UINT32 CpuIndex; + /// + /// Describes the Number of all max supported processors. + /// + UINT32 NumberOfProcessors; + /// + /// Pointer to SmBase address for each Processors. + /// + UINT64 SmBase[]; +} SMM_BASE_HOB_DATA; +#pragma pack() + +extern EFI_GUID gSmmBaseHobGuid; + +#endif diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index cff239d528..7003a2ba77 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -1,9 +1,9 @@ ## @file UefiCpuPkg.dec # This Package provides UEFI compatible CPU modules and libraries. # -# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -76,10 +76,13 @@ gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }} ## Include/Guid/MicrocodePatchHob.h gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }} + ## Include/Guid/SmmBaseHob.h + gSmmBaseHobGuid = { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73 }} + [Protocols] ## Include/Protocol/SmmCpuService.h gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }} gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }} -- 2.16.2.windows.1