From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.4368.1676528199491436564 for ; Wed, 15 Feb 2023 22:16:50 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=ObXcDFW6; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676528210; x=1708064210; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=FzIUAZMWeGiU8+Kd6v+rRyBI25VKs4518VWUcZWd8EY=; b=ObXcDFW6sDcHWw8Hy5XG/e0WamPvLQkNogXdklDt5p9Cjrhf4WLF6Svr fLL8OXjO+ZCrMM1gDC6P/BjyUxcxYF6ObPObciy/zn3mJ7ojc0xgWNkGz RtduHzoBHiEZqclr7cKX4ChLqbQRieApsFsS1rjKRdfK2h8+1WJMZzO0o UswbAB4nN11W5vLDZPKD5SFueO56fMwQpMAaRrO9TEpAxuZ5S+kJUpnOZ ZXOBTL4AmmWcjukN9IkHl9quaeEhnRtBysMKPA6cFg2IqyRHE71hSahGP XjNVNO7Qox4onygytFDYfpjUHdt2gTBRWg7oYA8og4+lz3Prs1cbC0BWG w==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="394057217" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="394057217" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 22:16:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="647556585" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="647556585" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga006.jf.intel.com with ESMTP; 15 Feb 2023 22:16:48 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [PATCH v9 5/6] UefiCpuPkg/SmmCpuFeaturesLib: Skip SMBASE configuration Date: Thu, 16 Feb 2023 14:16:32 +0800 Message-Id: <20230216061633.9196-6-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20230216061633.9196-1-jiaxin.wu@intel.com> References: <20230216061633.9196-1-jiaxin.wu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337 This patch is to avoid configure SMBASE if SmBase relocation has been done. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. No need to do the relocation in SmmCpuFeaturesInitializeProcessor(). Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu Reviewed-by: Ray Ni --- .../Library/SmmCpuFeaturesLib/CpuFeaturesLib.h | 2 ++ .../SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c | 25 ++++++++++++++++++---- .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 6 +++++- .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++- UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 3 +-- .../StandaloneMmCpuFeaturesLib.inf | 6 +++++- 6 files changed, 36 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h b/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h index fd3e902547..c2e4fbe96b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h @@ -7,15 +7,17 @@ **/ #ifndef CPU_FEATURES_LIB_H_ #define CPU_FEATURES_LIB_H_ +#include #include #include #include #include #include +#include /** Performs library initialization. This initialization function contains common functionality shared betwen all diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c index d5eaaa7a99..1a2c706fa1 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c @@ -1,9 +1,9 @@ /** @file Implementation shared across all library instances. -Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
Copyright (c) Microsoft Corporation.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -36,10 +36,16 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // Set default value to assume IA-32 Architectural MSRs are used // UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE; UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK; +// +// Indicate SmBase for each Processors has been relocated or not. If TRUE, +// means no need to do the relocation in SmmCpuFeaturesInitializeProcessor(). +// +BOOLEAN mSmmCpuFeaturesSmmRelocated; + // // Set default value to assume MTRRs need to be configured on each SMI // BOOLEAN mNeedConfigureMtrrs = TRUE; @@ -142,10 +148,16 @@ CpuFeaturesLibInitialization ( // // Allocate array for state of SMRR enable on all CPUs // mSmrrEnabled = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * GetCpuMaxLogicalProcessorNumber ()); ASSERT (mSmrrEnabled != NULL); + + // + // If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded + // in the SmBase array. + // + mSmmCpuFeaturesSmmRelocated = (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobGuid) != NULL); } /** Called during the very first SMI into System Management Mode to initialize CPU features, including SMBASE, for the currently executing CPU. Since this @@ -185,14 +197,19 @@ SmmCpuFeaturesInitializeProcessor ( UINT32 RegEdx; UINTN FamilyId; UINTN ModelId; // - // Configure SMBASE. + // No need to configure SMBASE if SmBase relocation has been done. // - CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); - CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + if (!mSmmCpuFeaturesSmmRelocated) { + // + // Configure SMBASE. + // + CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + } // // Intel(R) 64 and IA-32 Architectures Software Developer's Manual // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family // diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 9ac7dde78f..46ae2bf85e 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -1,9 +1,9 @@ ## @file # The CPU specific programming for PiSmmCpuDxeSmm module. # -# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## [Defines] @@ -31,10 +31,14 @@ [LibraryClasses] BaseLib PcdLib MemoryAllocationLib DebugLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOMETIMES_CONSUMES [FeaturePcd] diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf index 86d367e0a0..51322ff189 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf @@ -1,10 +1,10 @@ ## @file # The CPU specific programming for PiSmmCpuDxeSmm module when STM support # is included. # -# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## [Defines] @@ -62,10 +62,11 @@ [Guids] gMsegSmramGuid ## SOMETIMES_CONSUMES ## HOB gEfiAcpi20TableGuid ## SOMETIMES_CONSUMES ## SystemTable gEfiAcpi10TableGuid ## SOMETIMES_CONSUMES ## SystemTable + gSmmBaseHobGuid ## CONSUMES [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOMETIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize ## SOMETIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize ## SOMETIMES_CONSUMES diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c index 3cf162ada0..6cb1c515c0 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -1,16 +1,15 @@ /** @file SMM STM support functions - Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include #include -#include #include #include #include #include #include diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf index b1f60a5505..c836939d33 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf @@ -1,9 +1,9 @@ ## @file # Standalone MM CPU specific programming. # -# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
# Copyright (c) Microsoft Corporation.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -32,10 +32,14 @@ [LibraryClasses] BaseLib DebugLib MemoryAllocationLib PcdLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES [FixedPcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOMETIMES_CONSUMES [FeaturePcd] -- 2.16.2.windows.1