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* [PATCH v6] Update CPUID Leaf 06H to follow latest SDM.
@ 2023-02-17  8:24 Wang, William2
  2023-02-17  8:26 ` Ni, Ray
  0 siblings, 1 reply; 2+ messages in thread
From: Wang, William2 @ 2023-02-17  8:24 UTC (permalink / raw)
  To: devel
  Cc: William2 Wang, Michael D Kinney, Liming Gao, Ray Ni, Donald Kuo,
	Chandana C Kumar

From: William2 Wang <william2.wang@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4262

Update CPUID Leaf 06H to follow latest SDM.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Donald Kuo <Donald.Kuo@intel.com>
Cc: Chandana C Kumar <chandana.c.kumar@intel.com>
---
 MdePkg/Include/Register/Intel/Cpuid.h | 65 ++++++++++++++++++--
 1 file changed, 59 insertions(+), 6 deletions(-)

diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Register/Intel/Cpuid.h
index 350bf60252..a8d25671bd 100644
--- a/MdePkg/Include/Register/Intel/Cpuid.h
+++ b/MdePkg/Include/Register/Intel/Cpuid.h
@@ -1195,12 +1195,24 @@ typedef union {
     /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.
     ///
     UINT32    FastAccessMode                         : 1;
-    UINT32    Reserved4                              : 1;
+    ///
+    /// [Bit 19] IA32_HW_FEEDBACK_PTR MSR, IA32_HW_FEEDBACK_CONFIG MSR,
+    /// IA32_PACKAGE_THERM_STATUS MSR bit 26, and IA32_PACKAGE_THERM_INTERRUPT MSR bit 25 are supported if set.
+    UINT32    HW_FEEDBACK                            : 1;
     ///
     /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set.
     ///
     UINT32    IgnoringIdleLogicalProcessorHWPRequest : 1;
-    UINT32    Reserved5                              : 11;
+    UINT32    Reserved6                              : 2;
+    ///
+    /// [Bit 23] Intel Thread Director supported if set. IA32_HW_FEEDBACK_CHAR and
+    /// IA32_HW_FEEDBACK_THREAD_CONFIG MSRs are supported if set.
+    UINT32    ThreadDirector                         : 1;
+    ///
+    /// [Bit 24] IA32_THERM_INTERRUPT MSR bit 25 is supported if set.
+    ///
+    UINT32    IA32_THERM_INTERRUPT                   : 1;
+    UINT32    Reserved7                              : 7;
   } Bits;
   ///
   /// All bit fields as a 32-bit value
@@ -1244,15 +1256,21 @@ typedef union {
     /// processor performance (since last reset of the counters), as a percentage
     /// of the expected processor performance when running at the TSC frequency.
     ///
-    UINT32    HardwareCoordinationFeedback : 1;
-    UINT32    Reserved1                    : 2;
+    UINT32    HardwareCoordinationFeedback  : 1;
+    UINT32    Reserved1                     : 2;
     ///
     /// [Bit 3] If this bit is set, then the processor supports performance-energy
     /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
     /// (1B0H).
     ///
-    UINT32    PerformanceEnergyBias        : 1;
-    UINT32    Reserved2                    : 28;
+    UINT32    PerformanceEnergyBias         : 1;
+    UINT32    Reserved3                     : 4;
+    ///
+    /// {Bit 15:8] Number of Intel Thread Director classes supported by the processor. Information for that
+    /// many classes is written into the Intel Thread Director Table by the hardware.
+    ///
+    UINT32    NumberOfThreadDirectorClasses : 8;
+    UINT32    Reserved4                     : 16;
   } Bits;
   ///
   /// All bit fields as a 32-bit value
@@ -1260,6 +1278,41 @@ typedef union {
   UINT32    Uint32;
 } CPUID_THERMAL_POWER_MANAGEMENT_ECX;
 
+/**
+  CPUID Thermal and Power Management Information returned in EDX for CPUID leaf
+  #CPUID_THERMAL_POWER_MANAGEMENT.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// {Bits 7:0] Bitmap of supported hardware feedback interface capabilities.
+    ///   0 = When set to 1, indicates support for performance capability reporting.
+    ///   1 = When set to 1, indicates support for energy efficiency capability reporting.
+    ///   2-7 = Reserved
+    ///
+    UINT32    InterfaceCapability      : 8;
+    ///
+    /// {Bits 11:8] Enumerates the size of the hardware feedback interface structure in number of 4 KB pages;
+    /// add one to the return value to get the result.
+    ///
+    UINT32    InterfaceStructureSize4K : 4;
+    UINT32    Reserved                 : 4;
+    ///
+    /// {Bits 31:16] : Index (starting at 0) of this logical processor's row in the hardware feedback interface structure.
+    /// Note that on some parts the index may be same for multiple logical processors. On some parts the
+    /// indices may not be contiguous, i.e., there may be unused rows in the hardware feedback interface structure.
+    ///
+    UINT32    LogicalProcessorRowIndex : 16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_THERMAL_POWER_MANAGEMENT_EDX;
+
 /**
   CPUID Structured Extended Feature Flags Enumeration
 
-- 
2.34.1.windows.1


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