From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.6611.1676694496440192230 for ; Fri, 17 Feb 2023 20:28:16 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=nUVoHBCJ; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: andrei.warkentin@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676694496; x=1708230496; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=i7m22vBIItbEQ6U/x+xid/hLt09usPT/VWxhq2OIBwk=; b=nUVoHBCJv37OqEmmgbBuTnu/2VKe7fn6QXnwuI2FqS66xR1sDFfN6XyI WRgdUqzR2X1ejOZOLfr6gMr2KofVI7IuJzYIWr+vgoCcuBQ523vUIt8Z8 F4O05y88pPTPBCIgfq7ocLt/2BybPo/xbFxK+PY/9+RkFAvkj5YjMWr8X agAH+74f+acT4jjkVlDfqfQgNIHUDZshN8kD2lUmW1Flkm+vOZ3o0qJZZ fhjseAQ9nUa4zsAukQD4od2V0oK2yU7EUEfGtplDy2lJAoHt8NEgaAqF1 N/H4s/qq+dpZHx63Bbt42YEhd30SckM3Uw5nv2yqvqer1dAphMzp9B2hF g==; X-IronPort-AV: E=McAfee;i="6500,9779,10624"; a="332147130" X-IronPort-AV: E=Sophos;i="5.97,306,1669104000"; d="scan'208";a="332147130" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2023 20:28:15 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10624"; a="759614697" X-IronPort-AV: E=Sophos;i="5.97,306,1669104000"; d="scan'208";a="759614697" Received: from awarkent-mobl1.amr.corp.intel.com ([10.213.189.88]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2023 20:28:15 -0800 From: "Andrei Warkentin" To: devel@edk2.groups.io Cc: Andrei Warkentin , Sunil V L , Daniel Schaefer Subject: [edk2 1/1] RISCV: clean up exception handling Date: Fri, 17 Feb 2023 22:28:09 -0600 Message-Id: <20230218042809.851-1-andrei.warkentin@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable RegisterCpuInterruptHandler did not allow setting exception handlers for anything beyond the timer IRQ. Beyond that, it didn't meet the spec around handling of inputs. RiscVSupervisorModeTrapHandler now will invoke set handlers for both exceptions and interrupts. Two arrays of handlers are maintained - one for exceptions and one for interrupts. For unhandled traps, RiscVSupervisorModeTrapHandler dumps state using the now implemented DumpCpuContext. For EFI_SYSTEM_CONTEXT_RISCV64, extend this with the trapped PC address (SEPC), just like on AArch64 (ELR). This is necessary for X86EmulatorPkg to work as it allows a trap handler to return execution to a different place. Add SSTATUS/STVAL as well, at least for debugging purposes. There is no value in hiding this. Fix nested exception handling. Handler code should not be saving SIE (the value is saved in SSTATUS.SPIE) or directly restored (that's done by SRET). Save and restore the entire SSTATUS and STVAL, too. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Andrei Warkentin --- MdePkg/Include/Protocol/DebugSupport.h = | 23 ++- UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLi= b.h | 11 +- UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c = | 3 +- UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLi= b.c | 215 +++++++++++++++++--- UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/SupervisorTrapHandler= .S | 17 +- 5 files changed, 225 insertions(+), 44 deletions(-) diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protoc= ol/DebugSupport.h index 2b0ae2d1577b..0d94c409448c 100644 --- a/MdePkg/Include/Protocol/DebugSupport.h +++ b/MdePkg/Include/Protocol/DebugSupport.h @@ -613,11 +613,25 @@ typedef struct { #define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7=0D #define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8=0D #define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9=0D -#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10=0D +#define EXCEPT_RISCV_10 10=0D #define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11=0D +#define EXCEPT_RISCV_INST_ACCESS_PAGE_FAULT 12=0D +#define EXCEPT_RISCV_LOAD_ACCESS_PAGE_FAULT 13=0D +#define EXCEPT_RISCV_STORE_ACCESS_PAGE_FAULT 14=0D +#define EXCEPT_RISCV_MAX_EXCEPTIONS (EXCEPT_RISCV_STORE_ACC= ESS_PAGE_FAULT)=0D =0D -#define EXCEPT_RISCV_SOFTWARE_INT 0x0=0D -#define EXCEPT_RISCV_TIMER_INT 0x1=0D +///=0D +/// RISC-V processor exception types for interrupts.=0D +///=0D +#define EXCEPT_RISCV_IS_IRQ(x) ((x & 0x800000000000000= 0UL) !=3D 0)=0D +#define EXCEPT_RISCV_IRQ_INDEX(x) (x & 0x7FFFFFFFFFFFFFFF= UL)=0D +#define EXCEPT_RISCV_IRQ_0 0x8000000000000000UL=0D +#define EXCEPT_RISCV_IRQ_SOFT_FROM_SMODE 0x8000000000000001UL=0D +#define EXCEPT_RISCV_IRQ_2 0x8000000000000002UL=0D +#define EXCEPT_RISCV_IRQ_SOFT_FROM_MMODE 0x8000000000000003UL=0D +#define EXCEPT_RISCV_IRQ_4 0x8000000000000004UL=0D +#define EXCEPT_RISCV_IRQ_TIMER_FROM_SMODE 0x8000000000000005UL=0D +#define EXCEPT_RISCV_MAX_IRQS (EXCEPT_RISCV_IRQ_INDEX= (EXCEPT_RISCV_IRQ_TIMER_FROM_SMODE))=0D =0D typedef struct {=0D UINT64 X0;=0D @@ -652,6 +666,9 @@ typedef struct { UINT64 X29;=0D UINT64 X30;=0D UINT64 X31;=0D + UINT64 SEPC;=0D + UINT32 SSTATUS;=0D + UINT32 STVAL;=0D } EFI_SYSTEM_CONTEXT_RISCV64;=0D =0D //=0D diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExcept= ionHandlerLib.h b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuE= xceptionHandlerLib.h index 30f47e87552b..9b7e1304dd3b 100644 --- a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHand= lerLib.h +++ b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHand= lerLib.h @@ -59,7 +59,7 @@ SupervisorModeTrap ( #define SMODE_TRAP_REGS_t6 31=0D #define SMODE_TRAP_REGS_sepc 32=0D #define SMODE_TRAP_REGS_sstatus 33=0D -#define SMODE_TRAP_REGS_sie 34=0D +#define SMODE_TRAP_REGS_stval 34=0D #define SMODE_TRAP_REGS_last 35=0D =0D #define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINT= ER__)=0D @@ -68,7 +68,7 @@ SupervisorModeTrap ( #pragma pack(1)=0D typedef struct {=0D //=0D - // Below are follow the format of EFI_SYSTEM_CONTEXT=0D + // Below follow the format of EFI_SYSTEM_CONTEXT.=0D //=0D UINT64 zero;=0D UINT64 ra;=0D @@ -102,14 +102,9 @@ typedef struct { UINT64 t4;=0D UINT64 t5;=0D UINT64 t6;=0D - //=0D - // Below are the additional information to=0D - // EFI_SYSTEM_CONTEXT, private to supervisor mode trap=0D - // and not public to EFI environment.=0D - //=0D UINT64 sepc;=0D UINT64 sstatus;=0D - UINT64 sie;=0D + UINT64 stval;=0D } SMODE_TRAP_REGISTERS;=0D #pragma pack()=0D =0D diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c b/UefiCpuPkg/CpuTimerDxe= RiscV64/Timer.c index db153f715e60..0ecefddf1f18 100644 --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c @@ -271,7 +271,8 @@ TimerDriverInitialize ( //=0D // Install interrupt handler for RISC-V Timer.=0D //=0D - Status =3D mCpu->RegisterInterruptHandler (mCpu, EXCEPT_RISCV_TIMER_INT,= TimerInterruptHandler);=0D + Status =3D mCpu->RegisterInterruptHandler (mCpu, EXCEPT_RISCV_IRQ_TIMER_= FROM_SMODE,=0D + TimerInterruptHandler);=0D ASSERT_EFI_ERROR (Status);=0D =0D //=0D diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExcept= ionHandlerLib.c b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuE= xceptionHandlerLib.c index f1ee7d236aec..7e8be41cfb9b 100644 --- a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHand= lerLib.c +++ b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHand= lerLib.c @@ -11,11 +11,151 @@ #include =0D #include =0D #include =0D +#include =0D +#include =0D #include =0D -=0D #include "CpuExceptionHandlerLib.h"=0D =0D -STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];=0D +//=0D +// Define the maximum message length=0D +//=0D +#define MAX_DEBUG_MESSAGE_LENGTH 0x100=0D +=0D +STATIC EFI_CPU_INTERRUPT_HANDLER mExceptionHandlers[EXCEPT_RISCV_MAX_EXCEP= TIONS + 1];=0D +STATIC EFI_CPU_INTERRUPT_HANDLER mIrqHandlers[EXCEPT_RISCV_MAX_IRQS + 1];= =0D +=0D +STATIC CONST CHAR8 mExceptionOrIrqUnknown[] =3D "Unknown";=0D +STATIC CONST CHAR8 *mExceptionNameStr[EXCEPT_RISCV_MAX_EXCEPTIONS + 1] =3D= {=0D + "EXCEPT_RISCV_INST_MISALIGNED",=0D + "EXCEPT_RISCV_INST_ACCESS_FAULT",=0D + "EXCEPT_RISCV_ILLEGAL_INST",=0D + "EXCEPT_RISCV_BREAKPOINT",=0D + "EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED",=0D + "EXCEPT_RISCV_LOAD_ACCESS_FAULT",=0D + "EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED",=0D + "EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT",=0D + "EXCEPT_RISCV_ENV_CALL_FROM_UMODE",=0D + "EXCEPT_RISCV_ENV_CALL_FROM_SMODE",=0D + "EXCEPT_RISCV_ENV_CALL_FROM_HMODE",=0D + "EXCEPT_RISCV_ENV_CALL_FROM_MMODE",=0D + "EXCEPT_RISCV_INST_ACCESS_PAGE_FAULT",=0D + "EXCEPT_RISCV_INST_ACCESS_PAGE_FAULT",=0D + "EXCEPT_RISCV_STORE_ACCESS_PAGE_FAULT"=0D +};=0D +=0D +STATIC CONST CHAR8 *mIrqNameStr[EXCEPT_RISCV_MAX_IRQS + 1] =3D {=0D + "EXCEPT_RISCV_IRQ_0",=0D + "EXCEPT_RISCV_IRQ_SOFT_FROM_SMODE",=0D + "EXCEPT_RISCV_IRQ_2",=0D + "EXCEPT_RISCV_IRQ_SOFT_FROM_MMODE",=0D + "EXCEPT_RISCV_IRQ_4",=0D + "EXCEPT_RISCV_IRQ_TIMER_FROM_SMODE",=0D +};=0D +=0D +/**=0D + Prints a message to the serial port.=0D +=0D + @param Format Format string for the message to print.=0D + @param ... Variable argument list whose contents are accessed=0D + based on the format string specified by Format.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +InternalPrintMessage (=0D + IN CONST CHAR8 *Format,=0D + ...=0D + )=0D +{=0D + CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];=0D + VA_LIST Marker;=0D +=0D + //=0D + // Convert the message to an ASCII String=0D + //=0D + VA_START (Marker, Format);=0D + AsciiVSPrint (Buffer, sizeof (Buffer), Format, Marker);=0D + VA_END (Marker);=0D +=0D + //=0D + // Send the print string to a Serial Port=0D + //=0D + SerialPortWrite ((UINT8 *)Buffer, AsciiStrLen (Buffer));=0D +}=0D +=0D +/**=0D + Get ASCII format string exception name by exception type.=0D +=0D + @param ExceptionType Exception type.=0D +=0D + @return ASCII format string exception name.=0D +**/=0D +STATIC=0D +CONST CHAR8 *=0D +GetExceptionNameStr (=0D + IN EFI_EXCEPTION_TYPE ExceptionType=0D + )=0D +{=0D + if (EXCEPT_RISCV_IS_IRQ(ExceptionType)) {=0D + if (EXCEPT_RISCV_IRQ_INDEX(ExceptionType) > EXCEPT_RISCV_MAX_IRQS) {=0D + return mExceptionOrIrqUnknown;=0D + }=0D +=0D + return mIrqNameStr[EXCEPT_RISCV_IRQ_INDEX(ExceptionType)];=0D + }=0D +=0D + if (ExceptionType > EXCEPT_RISCV_MAX_EXCEPTIONS) {=0D + return mExceptionOrIrqUnknown;=0D + }=0D +=0D + return mExceptionNameStr[ExceptionType];=0D +}=0D +=0D +/**=0D + Display CPU information.=0D +=0D + @param ExceptionType Exception type.=0D + @param SystemContext Pointer to EFI_SYSTEM_CONTEXT.=0D +**/=0D +VOID=0D +EFIAPI=0D +DumpCpuContext (=0D + IN EFI_EXCEPTION_TYPE ExceptionType,=0D + IN EFI_SYSTEM_CONTEXT SystemContext=0D + )=0D +{=0D + UINTN Printed =3D 0;=0D + SMODE_TRAP_REGISTERS *Regs =3D (SMODE_TRAP_REGISTERS *)=0D + SystemContext.SystemContextRiscV64;=0D +=0D + InternalPrintMessage (=0D + "!!!! RISCV64 Exception Type - %016x(%a) !!!!\n",=0D + ExceptionType,=0D + GetExceptionNameStr (ExceptionType)=0D + );=0D +=0D +#define REGS() \= =0D + REG (t0); REG (t1); REG (t2); REG (t3); REG (t4); REG (t5); REG (t6); \= =0D + REG (s0); REG (s1); REG (s2); REG (s3); REG (s4); REG (s5); REG (s6); \= =0D + REG (s7); REG (s8); REG (s9); REG (s10); REG (s11); \= =0D + REG (a0); REG (a1); REG (a2); REG (a3); REG (a4); REG (a5); REG (a6); \= =0D + REG (a7); \= =0D + REG (zero); REG (ra); REG (sp); REG (gp); REG (tp); \= =0D + REG (sepc); REG (sstatus); REG (stval);=0D +=0D +#define REG(x) do { \=0D + InternalPrintMessage ("%7a =3D 0x%017lx%c", #x, Regs->x, \=0D + (++Printed % 2) ? L'\t' : L'\n'); \=0D + } while (0);=0D +=0D + REGS ();=0D + if (Printed % 2) {=0D + InternalPrintMessage ("\n");=0D + }=0D +=0D +#undef REG=0D +#undef REGS=0D +}=0D =0D /**=0D Initializes all CPU exceptions entries and provides the default exceptio= n handlers.=0D @@ -47,34 +187,56 @@ InitializeCpuExceptionHandlers ( Registers a function to be called from the processor interrupt handler.= =0D =0D This function registers and enables the handler specified by InterruptHa= ndler for a processor=0D - interrupt or exception type specified by InterruptType. If InterruptHand= ler is NULL, then the=0D - handler for the processor interrupt or exception type specified by Inter= ruptType is uninstalled.=0D + interrupt or exception type specified by ExceptionType. If InterruptHand= ler is NULL, then the=0D + handler for the processor interrupt or exception type specified by Excep= tionType is uninstalled.=0D The installed handler is called once for each processor interrupt or exc= eption.=0D NOTE: This function should be invoked after InitializeCpuExceptionHandle= rs() or=0D InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED retu= rned.=0D =0D - @param[in] InterruptType Defines which interrupt or exception to ho= ok.=0D + @param[in] ExceptionType Defines which interrupt or exception to ho= ok.=0D @param[in] InterruptHandler A pointer to a function of type EFI_CPU_IN= TERRUPT_HANDLER that is called=0D when a processor interrupt occurs. If this= parameter is NULL, then the handler=0D will be uninstalled.=0D =0D @retval EFI_SUCCESS The handler for the processor interrupt wa= s successfully installed or uninstalled.=0D - @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handle= r for InterruptType was=0D + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handle= r for ExceptionType was=0D previously installed.=0D - @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler fo= r InterruptType was not=0D + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler fo= r ExceptionType was not=0D previously installed.=0D - @retval EFI_UNSUPPORTED The interrupt specified by InterruptType i= s not supported,=0D + @retval EFI_UNSUPPORTED The interrupt specified by ExceptionType i= s not supported,=0D or this function is not supported.=0D **/=0D EFI_STATUS=0D EFIAPI=0D RegisterCpuInterruptHandler (=0D - IN EFI_EXCEPTION_TYPE InterruptType,=0D + IN EFI_EXCEPTION_TYPE ExceptionType,=0D IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D )=0D {=0D - DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, Interrupt= Type, InterruptHandler));=0D - mInterruptHandlers[InterruptType] =3D InterruptHandler;=0D + DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, Exception= Type, InterruptHandler));=0D + if (EXCEPT_RISCV_IS_IRQ(ExceptionType)) {=0D + if (EXCEPT_RISCV_IRQ_INDEX(ExceptionType) > EXCEPT_RISCV_MAX_IRQS) {=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + if (mIrqHandlers[EXCEPT_RISCV_IRQ_INDEX(ExceptionType)] !=3D NULL) {=0D + return EFI_ALREADY_STARTED;=0D + } else if (InterruptHandler =3D=3D NULL) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D + mIrqHandlers[EXCEPT_RISCV_IRQ_INDEX(ExceptionType)] =3D InterruptHandl= er;=0D + } else {=0D + if (ExceptionType > EXCEPT_RISCV_MAX_EXCEPTIONS) {=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + if (mExceptionHandlers[ExceptionType] !=3D NULL) {=0D + return EFI_ALREADY_STARTED;=0D + } else if (InterruptHandler =3D=3D NULL) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D + mExceptionHandlers[ExceptionType] =3D InterruptHandler;=0D + }=0D return EFI_SUCCESS;=0D }=0D =0D @@ -113,21 +275,28 @@ RiscVSupervisorModeTrapHandler ( SMODE_TRAP_REGISTERS *SmodeTrapReg=0D )=0D {=0D - UINTN SCause;=0D + EFI_EXCEPTION_TYPE ExceptionType;=0D EFI_SYSTEM_CONTEXT RiscVSystemContext;=0D =0D RiscVSystemContext.SystemContextRiscV64 =3D (EFI_SYSTEM_CONTEXT_RISCV64 = *)SmodeTrapReg;=0D - //=0D - // Check scasue register.=0D - //=0D - SCause =3D (UINTN)RiscVGetSupervisorTrapCause ();=0D - if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) !=3D 0) {=0D - //=0D - // This is interrupt event.=0D - //=0D - SCause &=3D ~(1UL << (sizeof (UINTN) * 8- 1));=0D - if ((SCause =3D=3D IRQ_S_TIMER) && (mInterruptHandlers[EXCEPT_RISCV_TI= MER_INT] !=3D NULL)) {=0D - mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, R= iscVSystemContext);=0D + ExceptionType =3D (UINTN)RiscVGetSupervisorTrapCause ();=0D +=0D + if (EXCEPT_RISCV_IS_IRQ(ExceptionType)) {=0D + UINTN IrqIndex =3D EXCEPT_RISCV_IRQ_INDEX(ExceptionType);=0D +=0D + if (IrqIndex <=3D EXCEPT_RISCV_MAX_IRQS &&=0D + mIrqHandlers[IrqIndex] !=3D NULL) {=0D + mIrqHandlers[IrqIndex] (ExceptionType, RiscVSystemContext);=0D + return;=0D + }=0D + } else {=0D + if (ExceptionType <=3D EXCEPT_RISCV_MAX_EXCEPTIONS &&=0D + mExceptionHandlers[ExceptionType] !=3D 0) {=0D + mExceptionHandlers[ExceptionType] (ExceptionType, RiscVSystemContext= );=0D + return;=0D }=0D }=0D +=0D + DumpCpuContext (ExceptionType, RiscVSystemContext);=0D + while (1);=0D }=0D diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/Superviso= rTrapHandler.S b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/Super= visorTrapHandler.S index 649c4c5becf4..45070b5cda04 100644 --- a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/SupervisorTrapHa= ndler.S +++ b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/SupervisorTrapHa= ndler.S @@ -20,14 +20,14 @@ SupervisorModeTrap: sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)=0D =0D csrr t0, CSR_SSTATUS=0D - and t0, t0, (SSTATUS_SIE | SSTATUS_SPIE)=0D sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)=0D csrr t0, CSR_SEPC=0D sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)=0D - csrr t0, CSR_SIE=0D - sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)=0D + csrr t0, CSR_STVAL=0D + sd t0, SMODE_TRAP_REGS_OFFSET(stval)(sp)=0D ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)=0D =0D + sd zero, SMODE_TRAP_REGS_OFFSET(zero)(sp)=0D sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)=0D sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)=0D sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)=0D @@ -59,6 +59,7 @@ SupervisorModeTrap: sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)=0D =0D /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */=0D + mv a0, sp=0D call RiscVSupervisorModeTrapHandler=0D =0D /* Restore all general regisers except SP */=0D @@ -66,6 +67,7 @@ SupervisorModeTrap: ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)=0D ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)=0D ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)=0D + ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)=0D ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)=0D ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)=0D ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)=0D @@ -93,13 +95,10 @@ SupervisorModeTrap: =0D ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)=0D csrw CSR_SEPC, t0=0D - ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)=0D - csrw CSR_SIE, t0=0D - csrr t0, CSR_SSTATUS=0D - ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)=0D - or t0, t0, t1=0D + ld t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)=0D csrw CSR_SSTATUS, t0=0D - ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)=0D + ld t0, SMODE_TRAP_REGS_OFFSET(stval)(sp)=0D + csrw CSR_STVAL, t0=0D ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)=0D addi sp, sp, SMODE_TRAP_REGS_SIZE=0D sret=0D --=20 2.25.1