From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web10.41728.1676986152142456783 for ; Tue, 21 Feb 2023 05:29:12 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=eCS+9RVv; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: evan.chai@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676986152; x=1708522152; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Ur26hlJi0vdSWRpO+jwNL7aAs227QhcPYLofx/Yu/Gs=; b=eCS+9RVvVpbC3WLjswJAqkTUPlPv4tzktBapNuH0XcNuv67e4tDFFCWn 9llLwEo9/UtOZcIJ5AuVf8buwoYSu3XJIueNrPmvB9JZKoMYqDTt3vZfa uuFUj4zBYlVgvkmO0uCeI5SSON91b+tufdMlYOGqVImoutRKRTwszYJYP fK6sjX3n5Dp120LzcTmzt7gHxqioqDAs307v2vWR7lBroFsK+9NlEDDH5 u/tGm7XJ5O8UkSMkq00IrpxwZUhDNsXqakOgOUhoxrITG+rv3qtg06OZ/ HkrSsBrb+WeYfTjbxYvA8w+WxiGX75QAi2ME+3PTh+PWFGZPTRMakOHva A==; X-IronPort-AV: E=McAfee;i="6500,9779,10627"; a="312999689" X-IronPort-AV: E=Sophos;i="5.97,315,1669104000"; d="scan'208";a="312999689" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Feb 2023 05:29:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10627"; a="704031521" X-IronPort-AV: E=Sophos;i="5.97,315,1669104000"; d="scan'208";a="704031521" Received: from evanccy.ccr.corp.intel.com ([10.238.200.73]) by orsmga001.jf.intel.com with ESMTP; 21 Feb 2023 05:29:10 -0800 From: "Chai, Evan" To: devel@edk2.groups.io Cc: "Chai, Evan" Subject: [edk2-devel] [PATCH edk2-platforms 1/1] Silicon/RISC-V: Fix a build failure in RiscVCpuLib Date: Tue, 21 Feb 2023 21:29:06 +0800 Message-Id: <20230221132906.1777-1-evan.chai@intel.com> X-Mailer: git-send-email 2.39.0.windows.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: "Chai, Evan" RiscVSetSupervisorAddressTranslationRegister() should be moved out from RiscVCpuLib since it had been merged to MdePkg/Include/Library/BaseLib.h, to avoid a multiple definition problem in building. Signed-off-by: Evan Chai --- .../RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h | 4 +--- Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 10 +--------- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Si= licon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h index efe85489..3331ea2f 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h @@ -2,6 +2,7 @@ RISC-V CPU library definitions.=0D =0D Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D @@ -96,9 +97,6 @@ RiscVReadMachineImplementId ( VOID=0D );=0D =0D -VOID=0D - RiscVSetSupervisorAddressTranslationRegister (UINT64);=0D -=0D VOID=0D RiscVSetSupervisorScratch (UINT64);=0D =0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/Silico= n/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S index e242c9b8..f5bff547 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S @@ -3,6 +3,7 @@ // RISC-V CPU functions.=0D //=0D // Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D +// Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D //=0D // SPDX-License-Identifier: BSD-2-Clause-Patent=0D //=0D @@ -132,12 +133,3 @@ ASM_FUNC (RiscVSetSupervisorStvec) ASM_FUNC (RiscVGetSupervisorStvec)=0D csrr a0, RISCV_CSR_SUPERVISOR_STVEC=0D ret=0D -=0D -//=0D -// Set Supervisor Address Translation and=0D -// Protection Register.=0D -//=0D -ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)=0D - csrw RISCV_CSR_SUPERVISOR_SATP, a0=0D - ret=0D -=0D --=20 2.34.1