From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web10.5673.1677196505855436099 for ; Thu, 23 Feb 2023 15:55:13 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=iD6CHhnw; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: andrei.warkentin@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677196513; x=1708732513; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O3Jkp0nC3L2usB3zsXYl/wUXufNxI7O19fhv3PebexU=; b=iD6CHhnwLi7BsLGkvmrEu/xHh4FM3xdWxZV5dIaM/vVBsHki5SwZ9Ubc 6hdG2cAhKbAVGB/wateVPhAD450YW7dQQHFMrBbTA788KSSMmJrxyT3x2 BODi7PgkRQXwy55+87hImCifayDyJX13I/GzMA7pp4sxmJWjMeYRSuy8y kahJvw6pknkcB7h5YGu1FqLWP1tUcdrIcgvP8o2fYC8sa4S62d1mT4PZZ iM0BxDps6C5JlUL4pI3iBiFaIgiTvwkzjgxURRivAklyAXbKRUN2rLKh/ 9zFFSaQBNjI+TNdwauf2agICrKHuJjvnlJrVnCVJx1XFZcVD7xc9YVLmM g==; X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="321549960" X-IronPort-AV: E=Sophos;i="5.97,322,1669104000"; d="scan'208";a="321549960" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 15:55:12 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="702984490" X-IronPort-AV: E=Sophos;i="5.97,322,1669104000"; d="scan'208";a="702984490" Received: from cywong-mobl.amr.corp.intel.com (HELO awarkent-mobl1.amr.corp.intel.com) ([10.212.53.4]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 15:55:12 -0800 From: "Andrei Warkentin" To: devel@edk2.groups.io Cc: Andrei Warkentin , Daniel Schaefer , Michael D Kinney , Liming Gao , Zhiguang Liu , Sunil V L Subject: [PATCH 3/7] MdePkg: BaseLib: don't log in RISCV InternalSwitchStack Date: Thu, 23 Feb 2023 17:54:50 -0600 Message-Id: <20230223235454.23556-4-andrei.warkentin@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230223235454.23556-1-andrei.warkentin@intel.com> References: <20230223235454.23556-1-andrei.warkentin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit InternalSwitchStack may be called with a TPL high enough for a DebugLib implementation to assert. Other arch implementations don't log either. Cc: Daniel Schaefer Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Reviewed-by: Sunil V L Signed-off-by: Andrei Warkentin --- MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c index cf646e498aba..b78424c16383 100644 --- a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c +++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c @@ -44,14 +44,6 @@ InternalSwitchStack ( { BASE_LIBRARY_JUMP_BUFFER JumpBuffer; - DEBUG (( - DEBUG_INFO, - "RISC-V InternalSwitchStack Entry:%x Context1:%x Context2:%x NewStack%x\n", \ - EntryPoint, - Context1, - Context2, - NewStack - )); JumpBuffer.RA = (UINTN)EntryPoint; JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *); JumpBuffer.S0 = (UINT64)(UINTN)Context1; -- 2.25.1