From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web10.17629.1677566711773320968 for ; Mon, 27 Feb 2023 22:45:12 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=O4ZvBlk5; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: evan.chai@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677566711; x=1709102711; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=eHRddIeyjv57QrHJjwRCn50b07GhuHQTskPXWbd/k7M=; b=O4ZvBlk5xPMOuvD6z83NjNeLmxOW84TtaH9OpJYc6wjp55gKOfcdKT6z +LAylYtUSftTAL7AEAyHMst0dZvDl7CEeaVVsOdN4sxcP1g6IBnsgb4og XzAQAHxQv06M8al5ybc8q2MLvLlCAsEIZJRrMn93HsCTgM+7EzpRMOLHS xt/E5x3rg19KZhgG+ztr8bp9kPnkoi0mKxTR5HSotjOiX/skdU/Suf765 vcwA5UJeLwkMGRLeoLJt+6RJEXhyHHsdJBc4AwVFvqqR/QSKIVYYb/z1c dH0uD7KuMEu7ixKjRVhmb4+GBXdGhJk0/+5yam/nrrHsneLqWt1s2yDmZ A==; X-IronPort-AV: E=McAfee;i="6500,9779,10634"; a="332787322" X-IronPort-AV: E=Sophos;i="5.98,221,1673942400"; d="scan'208";a="332787322" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2023 22:45:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10634"; a="763057451" X-IronPort-AV: E=Sophos;i="5.98,221,1673942400"; d="scan'208";a="763057451" Received: from evancy.sh.intel.com ([10.239.158.113]) by FMSMGA003.fm.intel.com with ESMTP; 27 Feb 2023 22:45:09 -0800 From: "Chai, Evan" To: devel@edk2.groups.io Subject: [edk2-devel] [PATCH edk2-platforms 1/1] Silicon/RiscVEdk2SbiLib.h: correct a duplicated macro definition Date: Tue, 28 Feb 2023 14:43:21 +0800 Message-Id: <20230228064321.20257-1-evan.chai@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable RiscVEdk2SbiLib.h has the same macro defination as BaseRiscVSbiLib.h, the latter one was merged to MdePkg. Signed-off-by: Evan Chai --- .../RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h = b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h index 36eb16e1..00fdca64 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h @@ -2,6 +2,7 @@ Library to call the RISC-V SBI ecalls=0D =0D Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -9,8 +10,8 @@ - Hart - Hardware Thread, similar to a CPU core=0D **/=0D =0D -#ifndef RISCV_SBI_LIB_H_=0D -#define RISCV_SBI_LIB_H_=0D +#ifndef RISCV_SBI_LIB2_H_=0D +#define RISCV_SBI_LIB2_H_=0D =0D #include =0D #include =0D --=20 2.34.1