From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web11.7656.1677793777872244982 for ; Thu, 02 Mar 2023 13:49:42 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=fU2yn5L3; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: andrei.warkentin@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677793782; x=1709329782; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s88JT143p/x68Y+kbKsT9Ceu+iqd3G3XYphqkN8cVL0=; b=fU2yn5L3klTEG3PNSlZMzdkwsJywPoga+c3tGyIRbRtqR/2sxeGahclc bT7VpZqNlKianPR8vqN5X6ZP9WYwNv6JGBR9VGbwkYndBvc8YRNl+feXg qQ1flkHjPytTYm5CR3zCHwmYm833AXVRI8J+ObVsMc1YWz9OyhxA/EOCF 3KVy9I5wuZgoJDLNHmFYHzUS1vhXyrAVoluILT/+I0spmZ/krYTRXWDqB 9l35utmuPs6yR26CCfoig033Tmkd74oVDH1suHNYkxM55JxrbkORwXelE yBT9abZJuBt2Hh+39f7WYZWqabFYB74LSQjkJZ3CeWwHrkHbNV3AhxlBI g==; X-IronPort-AV: E=McAfee;i="6500,9779,10637"; a="333584620" X-IronPort-AV: E=Sophos;i="5.98,228,1673942400"; d="scan'208";a="333584620" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2023 13:49:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10637"; a="1004321708" X-IronPort-AV: E=Sophos;i="5.98,228,1673942400"; d="scan'208";a="1004321708" Received: from mayurkum-mobl2.amr.corp.intel.com (HELO awarkent-mobl1.amr.corp.intel.com) ([10.213.175.186]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2023 13:49:41 -0800 From: "Andrei Warkentin" To: devel@edk2.groups.io Cc: Andrei Warkentin , Daniel Schaefer , Sunil V L Subject: [edk2 3/3] OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec Date: Thu, 2 Mar 2023 15:49:20 -0600 Message-Id: <20230302214920.13817-4-andrei.warkentin@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230302214920.13817-1-andrei.warkentin@intel.com> References: <20230302214920.13817-1-andrei.warkentin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit If the SerialPortLib had any initialization needed, this would be skipped in the RiscVVirt Sec. Follow the example seen elsewhere (ArmVirtPkg PrePi). Seen with BaseSerialPortLibRiscVSbi not using DBCN in Sec, yet using DBCN elsewhere. Cc: Daniel Schaefer Cc: Sunil V L Signed-off-by: Andrei Warkentin --- OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + OvmfPkg/RiscVVirt/Sec/SecMain.h | 1 + OvmfPkg/RiscVVirt/Sec/SecMain.c | 4 +++- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf b/OvmfPkg/RiscVVirt/Sec/SecMain.inf index aed35d3af596..0e2a5785e8a4 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf @@ -48,6 +48,7 @@ [LibraryClasses] FdtLib MemoryAllocationLib HobLib + SerialPortLib [Ppis] gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.h b/OvmfPkg/RiscVVirt/Sec/SecMain.h index 83a8058efe40..7c7650f0d298 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.h +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.h @@ -29,6 +29,7 @@ #include #include #include +#include #include /** diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c b/OvmfPkg/RiscVVirt/Sec/SecMain.c index adf73f2eb66c..db309ebdf1a3 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.c +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.c @@ -1,7 +1,7 @@ /** @file RISC-V SEC phase module for Qemu Virt. - Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.
Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -57,6 +57,8 @@ SecStartup ( UINT64 StackBase; UINT32 StackSize; + SerialPortInitialize (); + // // Report Status Code to indicate entering SEC core // -- 2.25.1