From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web10.19850.1677837828807486048 for ; Fri, 03 Mar 2023 02:03:54 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=kSXxTYEm; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677837834; x=1709373834; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pvU0JLq8D77HRw3MS0qVd9aveRxyknM7R0INbCanm6Q=; b=kSXxTYEmXDJOUgQk5AQhPegieOGv+4NXYSeeHNBJEZB1knhnb+cpVpVU Fyb4O9vJ1MeXMmZJufyYNJIPeB5mBgRzSit3VOD6adMHgJVqprFFrLSfJ BezMXhZwrW52dA8jks0f9A0vEpO2lES1B9oLj9/+La3i6GJ3wmyIxvGWV 7BOeZSlSGWkgYhPBsRuK5V1wHY1kNqELb0wABCQgBSejDzE4eWo95QORR ofV5sd6iOcC3GehExaIDLrdDFS8ZyA8VJvm8Oi8SAJQBT0VnWSWIHasV6 eZU2PIx7jB1Hiiq+KDtCrhuJ1baRwt1xsgjGzA5/rqsrwnZxoxexB0Sxf g==; X-IronPort-AV: E=McAfee;i="6500,9779,10637"; a="318831677" X-IronPort-AV: E=Sophos;i="5.98,230,1673942400"; d="scan'208";a="318831677" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2023 02:03:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10637"; a="818420998" X-IronPort-AV: E=Sophos;i="5.98,230,1673942400"; d="scan'208";a="818420998" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2023 02:03:52 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [PATCH 2/6] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue Date: Fri, 3 Mar 2023 18:03:32 +0800 Message-Id: <20230303100336.2138-3-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230303100336.2138-1-dun.tan@intel.com> References: <20230303100336.2138-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Fix the non-1:1 mapping issue in PageTableMap () of CpuPageTableLib Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index 47027917d9..d2f35aa375 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -258,6 +258,7 @@ PageTableLibMapInLevel ( UINTN BitStart; UINTN Index; IA32_PAGING_ENTRY *PagingEntry; + UINTN PagingEntryIndex; IA32_PAGING_ENTRY *CurrentPagingEntry; UINT64 RegionLength; UINT64 SubLength; @@ -288,6 +289,13 @@ PageTableLibMapInLevel ( LocalParentAttribute.Uint64 = ParentAttribute->Uint64; ParentAttribute = &LocalParentAttribute; + // + // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 21) or 4K (1 << 12). + // + BitStart = 12 + (Level - 1) * 9; + PagingEntryIndex = (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart, BitStart + 9 - 1); + RegionLength = REGION_LENGTH (Level); + // // ParentPagingEntry ONLY is deferenced for checking Present and MustBeOne bits // when Modify is FALSE. @@ -325,8 +333,11 @@ PageTableLibMapInLevel ( // the actual attributes of grand-parents when determing the memory type. // PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute (&ParentPagingEntry->PleB, ParentAttribute); - if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)) - == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))) + if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)) + == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))) && + ( (Mask->Bits.PageTableBaseAddress == 0) + || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) + PagingEntryIndex * RegionLength) + == (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset)))) { // // This function is called when the memory length is less than the region length of the parent level. @@ -353,8 +364,7 @@ PageTableLibMapInLevel ( // PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOneMask); - RegionLength = REGION_LENGTH (Level); - PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle); + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle); for (SubOffset = 0, Index = 0; Index < 512; Index++) { PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset; SubOffset += RegionLength; @@ -425,14 +435,11 @@ PageTableLibMapInLevel ( } // - // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 21) or 4K (1 << 12). // RegionStart: points to the linear address that's aligned on RegionLength and lower than (LinearAddress + Offset). // - BitStart = 12 + (Level - 1) * 9; - Index = (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart, BitStart + 9 - 1); - RegionLength = LShiftU64 (1, BitStart); - RegionMask = RegionLength - 1; - RegionStart = (LinearAddress + Offset) & ~RegionMask; + Index = PagingEntryIndex; + RegionMask = RegionLength - 1; + RegionStart = (LinearAddress + Offset) & ~RegionMask; ParentAttribute->Uint64 = PageTableLibGetPnleMapAttribute (&ParentPagingEntry->Pnle, ParentAttribute); -- 2.31.1.windows.1