From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web10.19850.1677837828807486048 for ; Fri, 03 Mar 2023 02:03:56 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=N1oiqPDV; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677837836; x=1709373836; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=19OcRA/DQddWarZu4VEB9rwoPMT+Hlji/waFYjZw57k=; b=N1oiqPDVUQ/ACrHi+9/6lw2FqOhDbBauM1VTjYqgWi6uCrrQHDzzXPie OnV7XoYD+nJLcA0vJu6cVwE5GIFL/el5wL7d+KrxOV0ztQ6uaCcoAqL/U IRgpEUKdHbg7JYdPFNJt7AcISnTNr7pBSNQNRpYYe2WCGD3e5URQ2Qh6n iVPTXLylZc7FkPJDbVnol5xHEhGsRASAmCjXwSBCD+/IWSBtGE2gke/G0 qJetVLkmhh5lcycMAafJN/mZNm6q6iKI7RfSRg/BfYESB3dZP8l5/o/fL KMMa9EouLnctjaDRx8Dt0Df0Al4Kw66ReUSvtn6s3fMVI+Y4kLA2AKAtC A==; X-IronPort-AV: E=McAfee;i="6500,9779,10637"; a="318831707" X-IronPort-AV: E=Sophos;i="5.98,230,1673942400"; d="scan'208";a="318831707" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2023 02:03:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10637"; a="818421017" X-IronPort-AV: E=Sophos;i="5.98,230,1673942400"; d="scan'208";a="818421017" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2023 02:03:54 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [PATCH 3/6] UefiCpuPkg/CpuPageTebleLib: Check input Mask in PageTableMap Date: Fri, 3 Mar 2023 18:03:33 +0800 Message-Id: <20230303100336.2138-4-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230303100336.2138-1-dun.tan@intel.com> References: <20230303100336.2138-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When creating new page table or mapping not-present range in existing page table, we need to make sure all the non-reserved fields of input Mask are not 0. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index d2f35aa375..21fdfb53c1 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -214,6 +214,28 @@ PageTableLibSetPnle ( Pnle->Bits.CacheDisabled = 0; } +/** + Check if any Non-Reserved field of Mask is 0. When creating new page table or mapping not-present + range, we need to make sure all the non-reserved fields of input Mask are not 0. + + @param[in] Mask The mask used for attribute to check. +**/ +RETURN_STATUS +CheckMaskNonReservedBit ( + IN IA32_MAP_ATTRIBUTE *Mask + ) +{ + if ((Mask->Bits.Present == 0) || (Mask->Bits.ReadWrite == 0) || (Mask->Bits.UserSupervisor == 0) || + (Mask->Bits.WriteThrough == 0) || (Mask->Bits.CacheDisabled == 0) || (Mask->Bits.Accessed == 0) || + (Mask->Bits.Dirty == 0) || (Mask->Bits.Pat == 0) || (Mask->Bits.Global == 0) || + (Mask->Bits.PageTableBaseAddress == 0) || (Mask->Bits.ProtectionKey == 0) || (Mask->Bits.Nx == 0)) + { + return RETURN_INVALID_PARAMETER; + } + + return RETURN_SUCCESS; +} + /** Update page table to map [LinearAddress, LinearAddress + Length) with specified attribute in the specified level. @@ -259,6 +281,7 @@ PageTableLibMapInLevel ( UINTN Index; IA32_PAGING_ENTRY *PagingEntry; UINTN PagingEntryIndex; + UINTN PagingEntryIndexLimit; IA32_PAGING_ENTRY *CurrentPagingEntry; UINT64 RegionLength; UINT64 SubLength; @@ -302,6 +325,15 @@ PageTableLibMapInLevel ( // if (ParentPagingEntry->Pce.Present == 0) { + // + // [LinearAddress, LinearAddress + Length] contains not-present range, we need to + // make sure all the non-reserved fields of Mask are not 0. + // + Status = CheckMaskNonReservedBit (Mask); + if (RETURN_ERROR (Status)) { + return Status; + } + // // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. @@ -371,6 +403,23 @@ PageTableLibMapInLevel ( } } } else { + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle); + PagingEntryIndexLimit = (UINTN)BitFieldRead64 (LinearAddress + Length - 1, BitStart, BitStart + 9 - 1); + for (Index = PagingEntryIndex; Index <= PagingEntryIndexLimit; Index++) { + if (PagingEntry[Index].Pce.Present == 0) { + // + // [LinearAddress, LinearAddress + Length] contains not-present range, we need to + // make sure all the non-reserved fields of Mask are not 0. + // + Status = CheckMaskNonReservedBit (Mask); + if (RETURN_ERROR (Status)) { + return Status; + } + + break; + } + } + // // It's a non-leaf entry // @@ -418,7 +467,6 @@ PageTableLibMapInLevel ( // Update child entries to use restrictive attribute inherited from parent. // e.g.: Set PDE[0-255].ReadWrite = 0 // - PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle); for (Index = 0; Index < 512; Index++) { if (PagingEntry[Index].Pce.Present == 0) { continue; -- 2.31.1.windows.1