From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.30787.1677866666579516306 for ; Fri, 03 Mar 2023 10:04:27 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=QJBGBGq7; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: andrei.warkentin@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677866667; x=1709402667; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s88JT143p/x68Y+kbKsT9Ceu+iqd3G3XYphqkN8cVL0=; b=QJBGBGq7hMWsu99uQA1/myS1cI3I6zDnMH6LEqNmqU9oSTml7XxyubAi x+fOyPoYnjxZ3/0pIyC/Rr9/MSpWi1bzKifIf8+Sj39UP/KahKsTnj27R wT47EEAl1qovTRyaVTB1jKRKlS/4JGNC6cyfIx3MpQHjRx8iXdkx29bnb +9R9GRMXU4rhgEsHSKMswfZ/hDLqYC7Sqd7R6hnqeMGcQbdGsK3t8S3wj vYwtMSGDr5DaZptWnl3/Ic5jSNnOsNk7Sw7sVuHVGWa79t1MCouMoGreM +ZFPLiT3quiTr5C/0OlI0xvDbWg8A4O/OSO3iM8lgI4cbhGaUMMIPyoL9 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10638"; a="332593504" X-IronPort-AV: E=Sophos;i="5.98,231,1673942400"; d="scan'208";a="332593504" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2023 10:04:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10638"; a="849541902" X-IronPort-AV: E=Sophos;i="5.98,231,1673942400"; d="scan'208";a="849541902" Received: from snainar-mobl1.amr.corp.intel.com (HELO awarkent-mobl1.amr.corp.intel.com) ([10.212.75.200]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2023 10:04:23 -0800 From: "Andrei Warkentin" To: devel@edk2.groups.io Cc: Andrei Warkentin , Daniel Schaefer , Sunil V L Subject: [edk2 3/3] OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec Date: Fri, 3 Mar 2023 12:04:10 -0600 Message-Id: <20230303180410.6344-4-andrei.warkentin@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303180410.6344-1-andrei.warkentin@intel.com> References: <20230303180410.6344-1-andrei.warkentin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit If the SerialPortLib had any initialization needed, this would be skipped in the RiscVVirt Sec. Follow the example seen elsewhere (ArmVirtPkg PrePi). Seen with BaseSerialPortLibRiscVSbi not using DBCN in Sec, yet using DBCN elsewhere. Cc: Daniel Schaefer Cc: Sunil V L Signed-off-by: Andrei Warkentin --- OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + OvmfPkg/RiscVVirt/Sec/SecMain.h | 1 + OvmfPkg/RiscVVirt/Sec/SecMain.c | 4 +++- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf b/OvmfPkg/RiscVVirt/Sec/SecMain.inf index aed35d3af596..0e2a5785e8a4 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf @@ -48,6 +48,7 @@ [LibraryClasses] FdtLib MemoryAllocationLib HobLib + SerialPortLib [Ppis] gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.h b/OvmfPkg/RiscVVirt/Sec/SecMain.h index 83a8058efe40..7c7650f0d298 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.h +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.h @@ -29,6 +29,7 @@ #include #include #include +#include #include /** diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c b/OvmfPkg/RiscVVirt/Sec/SecMain.c index adf73f2eb66c..db309ebdf1a3 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.c +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.c @@ -1,7 +1,7 @@ /** @file RISC-V SEC phase module for Qemu Virt. - Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.
Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -57,6 +57,8 @@ SecStartup ( UINT64 StackBase; UINT32 StackSize; + SerialPortInitialize (); + // // Report Status Code to indicate entering SEC core // -- 2.25.1