From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) by mx.groups.io with SMTP id smtpd.web11.1139.1678124006645284517 for ; Mon, 06 Mar 2023 09:33:26 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=OI0ZtkSv; spf=pass (domain: ventanamicro.com, ip: 209.85.210.179, mailfrom: tphan@ventanamicro.com) Received: by mail-pf1-f179.google.com with SMTP id a7so6310565pfx.10 for ; Mon, 06 Mar 2023 09:33:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678124005; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=oIeF19QCMr1to7gUjQEprNtaLr8jZo+tKYWT+AEIcsE=; b=OI0ZtkSvAqsKoSazExDaLL7yvh68t3XsCTGngEkZDGEjBvLAY1PU8xkWd4wHRTxm47 8lbrKsitwn1SWeRJXia+CbLbpoGN0iWcnQgGWYfjWHfi3eP1x4501lmD/ohQZNneMCok ijCrFY8xWbAP/+l9AV9jd9yxn+Swy9BhPbpTZ2HaW2YL6Fb9jtrxMNiMTLibA8bQNEPe cjmQd7aX7YIcoDKj0rR1K2vkTjtNirtmwd+ldCy8us6+bePXsBMHU0K23Xi0y8WwOWWQ IJTGGhZ0hury2Y2Hc+Nvfi+Qo57yJ0dspzg/GwiP5GwxYfleaQmsnv4/ft65pHilMPlq 1hvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678124005; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=oIeF19QCMr1to7gUjQEprNtaLr8jZo+tKYWT+AEIcsE=; b=GDPDuMeSYlWHLZImyCnpDj1TDwpHxgyjeIPKEtE0Hq7fIxuz2q5L7bg+5x2FYtjtRG cjqP82de9QhmDjuwB8ag0pxnSlLvrjM0VFmrq6u3zGZGxWYvAGgx24DBJSfy/WrjFXid 7d1A6cvXobpWn3uUDKayvw2+A5CXJT+LylTKB7cxUC6FXllJGT3b94YIgIlqg5re7ozI bak9+FiqODlr2Ull5zXBx1NRdkYAMVA+QYpjJJstAtEmBXpPclCwEEIdmg+VR+OVdjyq alYi5VX8DCP/+j0ZmuYKjo/jFWI0gnPWC0Wk4uuw9TGeA+zaB8nyAmER1DzdA+OTXC2Y ydog== X-Gm-Message-State: AO0yUKUgZFrmRvC7XmYuouem2frSLR2RQ89AFYi7Fht0BHx90mA/15hZ g1m2/hFJrw14FxszvNsB3a2yzFyKpdLE0wmRBPfwug== X-Google-Smtp-Source: AK7set82GGyU14rnPNupBjJzU2UzUMl5IEatiTxO967fsnmvVn8QtoHEXNpFM6iKGNTSML94rdtAaw== X-Received: by 2002:aa7:9546:0:b0:5e3:2f9b:b5e8 with SMTP id w6-20020aa79546000000b005e32f9bb5e8mr8539736pfq.4.1678124005614; Mon, 06 Mar 2023 09:33:25 -0800 (PST) Return-Path: Received: from localhost.localdomain (c-174-50-177-95.hsd1.ca.comcast.net. [174.50.177.95]) by smtp.gmail.com with ESMTPSA id v6-20020aa78506000000b005dd975176c3sm6579722pfn.53.2023.03.06.09.33.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 09:33:25 -0800 (PST) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, Tuan Phan Subject: [PATCH 0/7] RISC-V: Add MMU support Date: Mon, 6 Mar 2023 09:33:09 -0800 Message-Id: <20230306173316.10319-1-tphan@ventanamicro.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds MMU support for RISC-V. Only SV39/48/57 modes are supported and tested. The MMU is required to support setting page attribute which is the first basic step to support security booting on RISC-V. There are three parts: 1. Add MMU core to UefiCpuPkg. MMU will be enabled during CpuDxe initialization. 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to GCD if already done. 3. Enable MMU for RiscVVirt platform and populating its device resources in SEC phase. All resources should be populated in HOB or added to GCD by driver before accessing them when MMU enabled. Tuan Phan (7): MdePkg/BaseLib: RISC-V: Support getting satp register value MdePkg/Register: RISC-V: Add satp mode bits shift definition UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices OvmfPkg/RiscVVirt: Enable MMU with SV39 mode MdePkg/Include/Library/BaseLib.h | 5 + .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + .../VirtNorFlashStaticLib.c | 3 +- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/Sec/Memory.c | 17 - OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++ OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 10 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 5 + UefiCpuPkg/CpuDxeRiscV64/Mmu.c | 493 ++++++++++++++++++ UefiCpuPkg/CpuDxeRiscV64/Mmu.h | 33 ++ UefiCpuPkg/CpuDxeRiscV64/MmuCore.S | 29 ++ UefiCpuPkg/UefiCpuPkg.dec | 8 + 16 files changed, 676 insertions(+), 32 deletions(-) create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.c create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.h create mode 100644 UefiCpuPkg/CpuDxeRiscV64/MmuCore.S -- 2.25.1