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From: "Tuan Phan" <tphan@ventanamicro.com>
To: devel@edk2.groups.io
Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn,
	zhiguang.liu@intel.com, sunilvl@ventanamicro.com,
	git@danielschaefer.me, andrei.warkentin@intel.com,
	Tuan Phan <tphan@ventanamicro.com>
Subject: [PATCH 6/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices
Date: Mon,  6 Mar 2023 09:33:15 -0800	[thread overview]
Message-ID: <20230306173316.10319-7-tphan@ventanamicro.com> (raw)
In-Reply-To: <20230306173316.10319-1-tphan@ventanamicro.com>

Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart, flash base address are being accessing
directly in some core modules.

Those resources should be populated to HOB in SEC phase so they are
added to GCD before anyone can access them.

Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
---
 OvmfPkg/RiscVVirt/Sec/Platform.c  | 62 +++++++++++++++++++++++++++++++
 OvmfPkg/RiscVVirt/Sec/SecMain.inf |  1 +
 2 files changed, 63 insertions(+)

diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c b/OvmfPkg/RiscVVirt/Sec/Platform.c
index e8fd126cf800..63bc21eb3f60 100644
--- a/OvmfPkg/RiscVVirt/Sec/Platform.c
+++ b/OvmfPkg/RiscVVirt/Sec/Platform.c
@@ -21,6 +21,63 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <libfdt.h>
 #include <Guid/FdtHob.h>
 
+/**
+  Build memory map I/O range resource HOB using the
+  base address and size.
+
+  @param  MemoryBase     Memory map I/O base.
+  @param  MemorySize     Memory map I/O size.
+
+**/
+STATIC
+VOID
+AddIoMemoryBaseSizeHob (
+  EFI_PHYSICAL_ADDRESS  MemoryBase,
+  UINT64                MemorySize
+  )
+{
+  /* Align to EFI_PAGE_SIZE */
+  MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
+  BuildResourceDescriptorHob (
+    EFI_RESOURCE_MEMORY_MAPPED_IO,
+    EFI_RESOURCE_ATTRIBUTE_PRESENT     |
+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+    EFI_RESOURCE_ATTRIBUTE_TESTED,
+    MemoryBase,
+    MemorySize
+    );
+}
+
+/**
+  Populate IO resources from FDT that not added to GCD by its
+  driver in the DXE phase. 
+
+  @param  FdtBase       Fdt base address
+  @param  Compatible    Compatible string
+
+**/
+STATIC
+VOID
+PopulateIoResources (
+  VOID          *FdtBase,
+  CONST CHAR8*  Compatible
+  )
+{
+  UINT64  *Reg;
+  INT32   Node, LenP;
+
+  Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
+  while (Node != -FDT_ERR_NOTFOUND) {
+    Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", &LenP);
+    if (Reg) {
+      ASSERT (LenP == (2 * sizeof (UINT64)));
+      AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1]));
+    }
+    Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible);
+  }
+}
+
 /**
   @retval EFI_SUCCESS            The address of FDT is passed in HOB.
           EFI_UNSUPPORTED        Can't locate FDT.
@@ -80,5 +137,10 @@ PlatformPeimInitialization (
 
   BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSize));
 
+  PopulateIoResources (Base, "ns16550a");
+  PopulateIoResources (Base, "qemu,fw-cfg-mmio");
+  PopulateIoResources (Base, "virtio,mmio");
+  AddIoMemoryBaseSizeHob (PcdGet32 (PcdOvmfFdBaseAddress), PcdGet32 (PcdOvmfFirmwareFdSize));
+
   return EFI_SUCCESS;
 }
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
index aed35d3af596..e1f562264eea 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
@@ -61,6 +61,7 @@
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize
 
 [Guids]
   gFdtHobGuid
-- 
2.25.1


  parent reply	other threads:[~2023-03-06 17:33 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-06 17:33 [PATCH 0/7] RISC-V: Add MMU support Tuan Phan
2023-03-06 17:33 ` [PATCH 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value Tuan Phan
2023-03-06 17:33 ` [PATCH 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition Tuan Phan
2023-03-06 17:33 ` [PATCH 3/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode Tuan Phan
2023-03-06 17:33 ` [PATCH 4/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size Tuan Phan
2023-03-06 17:33 ` [PATCH 5/7] OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists Tuan Phan
2023-03-06 17:53   ` [edk2-devel] " Ard Biesheuvel
2023-05-24 18:13     ` Tuan Phan
2023-05-25 14:27       ` Ard Biesheuvel
2023-05-25 14:44         ` Tuan Phan
2023-03-06 17:33 ` Tuan Phan [this message]
2023-03-06 17:33 ` [PATCH 7/7] OvmfPkg/RiscVVirt: Enable MMU with SV39 mode Tuan Phan
2023-03-09  0:46   ` Andrei Warkentin
2023-03-09 19:19 ` [PATCH 0/7] RISC-V: Add MMU support Tuan Phan
2023-03-09 21:34   ` Andrei Warkentin
2023-03-10 22:20     ` Tuan Phan

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