From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) by mx.groups.io with SMTP id smtpd.web10.1082.1678124011746371711 for ; Mon, 06 Mar 2023 09:33:35 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=GKVl3Fbw; spf=pass (domain: ventanamicro.com, ip: 209.85.216.53, mailfrom: tphan@ventanamicro.com) Received: by mail-pj1-f53.google.com with SMTP id l1so10556149pjt.2 for ; Mon, 06 Mar 2023 09:33:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678124014; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TCSGbNgZaUmvsbZKxcWa2YwMrRC0G3uvxYo6M61jl+0=; b=GKVl3FbwTf7as2XSUF5zecXmhc7Q+4DwgPi9bdpKNYfmLdHqjH71W7GZ3j9R42xost wsPxva8V6p5Tm75zlq991oG93Vb5BJ9KCjKjx+Kq1l7HFF8wE8WH2mZdJzcMy4Y/zq9j g2nSOTwEHB19R4lrDnLxAs7BK+nDvj1dNn6hGXoHL6YfK5ikiu2Qow4At6NcjPTSLb1M 4pV/s/y/MjMOM58WLrRuv9eJ1xJ5Ys3KqrmkSrF1jrtIsYfgwgHMrohG+G0LHqeQ40Z9 PDD1dx6M3hGmyPUgyvboCqL0r4977UNREXrwsm2/d6bQkcHPPienfZWFl0tGjvNNaAOv zixA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678124014; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TCSGbNgZaUmvsbZKxcWa2YwMrRC0G3uvxYo6M61jl+0=; b=ruwi+KBy+cHYB1h0b1ozd9rvnuRpx0/Yz2KXYuvsAuLYJQaOcg70rPEYBQ8V4Gv1LH /S9G/v0azAMOz1xnAm659wcq6SNk4bDlAbVBgUD8TL9tSr0ROaYpYjJTNqj+5Vwu/2dl Is5UkucLpAhBNgHy+8izDkpuY6o110rvz19wvQe5C0hngUo4jsw7l7TE1UC2mY3oEkYD bZFg/95wTZ4he8vSjQ3oQ9TKmDA0VD7VEJNos9mFB4FoiOnox/lQ0GZGQoHVJbV/4Xoy 19e9oPZwqJnsvnwAA+X0R67rM/IaJ7IDu4mz/A3Tc4JrROKZOM8DlshSrvbUEv98DW1n Cwug== X-Gm-Message-State: AO0yUKXFE6MtVtEZjsXfrT5l1DtUOWSUMUJUABoPXmszVTu0eOB5vMM8 esWf1TTSW/1x/s6DUqGnu8tkgXKE4FntXRLqWc78HQ== X-Google-Smtp-Source: AK7set8vqoIPwJle0r1EwnJQkp8LgewzTU1b1lCEvsFIMPZV8LK5qJ59VZUz2JJRXHm3p/as1CJWrQ== X-Received: by 2002:a05:6a20:7d8b:b0:cc:39c5:1241 with SMTP id v11-20020a056a207d8b00b000cc39c51241mr16929826pzj.16.1678124014391; Mon, 06 Mar 2023 09:33:34 -0800 (PST) Return-Path: Received: from localhost.localdomain (c-174-50-177-95.hsd1.ca.comcast.net. [174.50.177.95]) by smtp.gmail.com with ESMTPSA id v6-20020aa78506000000b005dd975176c3sm6579722pfn.53.2023.03.06.09.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 09:33:34 -0800 (PST) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, Tuan Phan Subject: [PATCH 7/7] OvmfPkg/RiscVVirt: Enable MMU with SV39 mode Date: Mon, 6 Mar 2023 09:33:16 -0800 Message-Id: <20230306173316.10319-8-tphan@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306173316.10319-1-tphan@ventanamicro.com> References: <20230306173316.10319-1-tphan@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable As MMU will be enabled in CpuDxe, remove the code that set up satp mode in SEC phase. Enable SV39 as default mode. Signed-off-by: Tuan Phan --- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/Sec/Memory.c | 17 ----------------- 2 files changed, 1 insertion(+), 17 deletions(-) diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVV= irt.dsc.inc index 731f54f73f81..ef268481ca07 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc @@ -207,6 +207,7 @@ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0=0D gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000=0D gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVSatpMode|8=0D =0D # DEBUG_ASSERT_ENABLED 0x01=0D # DEBUG_PRINT_ENABLED 0x02=0D diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c index 70935b07b56b..0b589cd1d071 100644 --- a/OvmfPkg/RiscVVirt/Sec/Memory.c +++ b/OvmfPkg/RiscVVirt/Sec/Memory.c @@ -110,21 +110,6 @@ AddMemoryRangeHob ( AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));=0D }=0D =0D -/**=0D - Configure MMU=0D -**/=0D -STATIC=0D -VOID=0D -InitMmu (=0D - )=0D -{=0D - //=0D - // Set supervisor translation mode to Bare mode=0D - //=0D - RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 6= 0);=0D - DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.= \n", __FUNCTION__));=0D -}=0D -=0D /**=0D Publish system RAM and reserve memory regions.=0D =0D @@ -255,8 +240,6 @@ MemoryPeimInitialization ( }=0D }=0D =0D - InitMmu ();=0D -=0D BuildMemoryTypeInformationHob ();=0D =0D return EFI_SUCCESS;=0D --=20 2.25.1