From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web10.1898.1678137984252750213 for ; Mon, 06 Mar 2023 13:26:24 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=G3a5pxlx; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: andrei.warkentin@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678137984; x=1709673984; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=ypqILBH9jB9HDVZASQglyRtrZT6kxbOFGzFkEtNdxms=; b=G3a5pxlxrTj3ikoFqE5o9EJ54USSwS/MnOAXkas8A7TLA0LCPA9yp5tf X1dpb5FSoAEVjdx3eTltuKtSP3cyZk3RLsxHOPevJZuWue7Tah/pKYmE3 qcEHMjy726k4dqAoKI9+RfHbrvZrm+JrRP7Ok7kP3c3OI2R9r2xbRJOFG WhbNkjrPVcGEPXpYbGhtrCB7AeUtNJJIVRN3j7BBhu5N6iGi7Jucz3PEy OQMaJEKXcZYIZZbf3ygh8HqUfrFnUBz6B/vqjAhIS27AmJm+tZtZfLPDp ZA4c/aRW+kgy70fox9RcsshoTyCz9esQ9oWH/yHv9UOYI/AqSa0CMHnkH w==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="315335507" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="315335507" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 13:26:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="819444246" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="819444246" Received: from awarkent-mobl1.amr.corp.intel.com ([10.212.90.17]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 13:26:23 -0800 From: "Andrei Warkentin" To: devel@edk2.groups.io Cc: Andrei Warkentin Subject: [edk2 0/7] v3 Assorted fixes to core RISC-V and RiscVVirt Date: Mon, 6 Mar 2023 15:26:08 -0600 Message-Id: <20230306212615.7400-1-andrei.warkentin@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Dear all, Please find the following patches for your reviewing pleasure. Sunil suggested I put these into a single patch set, instead of sending out these separately. This patch set is also available at https://github.com/andreiw/edk2-rv-wip/tree/patchset-1 Andrei Warkentin (7): OvmfPkg: RiscVVirt: add SATA support MdePkg: BasePeCoffLib: Allow AArch64 and x64 images in ImageFormatSupported MdePkg: BaseLib: don't log in RISCV InternalSwitchStack MdePkg: BaseCpuLib: Fix RISCV CpuSleep symbol name. MdeModulePkg: Dxe: add RISCV64 to mMachineTypeInfo UefiCpuPkg: CpuTimerDxeRiscV64: fix tick duration accounting UefiCpuPkg: BaseRiscV64CpuExceptionHandlerLib: clean up exception handling OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 7 + OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 7 + MdePkg/Include/Protocol/DebugSupport.h | 32 ++- UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLib.h | 11 +- MdeModulePkg/Core/Dxe/Image/Image.c | 3 +- MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c | 8 - MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 9 +- UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 39 ++-- UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLib.c | 235 ++++++++++++++++++-- MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 4 +- UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/SupervisorTrapHandler.S | 17 +- 11 files changed, 302 insertions(+), 70 deletions(-) -- 2.25.1