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From: "Andrei Warkentin" <andrei.warkentin@intel.com>
To: devel@edk2.groups.io
Cc: Andrei Warkentin <andrei.warkentin@intel.com>,
	Daniel Schaefer <git@danielschaefer.me>,
	Michael D Kinney <michael.d.kinney@intel.com>,
	Liming Gao <gaoliming@byosoft.com.cn>,
	Zhiguang Liu <zhiguang.liu@intel.com>,
	Sunil V L <sunilvl@ventanamicro.com>
Subject: [edk2 3/7] MdePkg: BaseLib: don't log in RISCV InternalSwitchStack
Date: Mon,  6 Mar 2023 15:26:11 -0600	[thread overview]
Message-ID: <20230306212615.7400-4-andrei.warkentin@intel.com> (raw)
In-Reply-To: <20230306212615.7400-1-andrei.warkentin@intel.com>

InternalSwitchStack may be called with a TPL high
enough for a DebugLib implementation to assert.

Other arch implementations don't log either.

Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
---
 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
index cf646e498aba..b78424c16383 100644
--- a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
+++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
@@ -44,14 +44,6 @@ InternalSwitchStack (
 {
   BASE_LIBRARY_JUMP_BUFFER  JumpBuffer;
 
-  DEBUG ((
-    DEBUG_INFO,
-    "RISC-V InternalSwitchStack Entry:%x Context1:%x Context2:%x NewStack%x\n", \
-    EntryPoint,
-    Context1,
-    Context2,
-    NewStack
-    ));
   JumpBuffer.RA = (UINTN)EntryPoint;
   JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *);
   JumpBuffer.S0 = (UINT64)(UINTN)Context1;
-- 
2.25.1


  parent reply	other threads:[~2023-03-06 21:26 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-06 21:26 [edk2 0/7] v3 Assorted fixes to core RISC-V and RiscVVirt Andrei Warkentin
2023-03-06 21:26 ` [edk2 1/7] OvmfPkg: RiscVVirt: add SATA support Andrei Warkentin
2023-03-06 21:26 ` [edk2 2/7] MdePkg: BasePeCoffLib: Allow AArch64 and x64 images in ImageFormatSupported Andrei Warkentin
2023-03-06 21:26 ` Andrei Warkentin [this message]
2023-03-06 21:26 ` [edk2 4/7] MdePkg: BaseCpuLib: Fix RISCV CpuSleep symbol name Andrei Warkentin
2023-03-06 21:26 ` [edk2 5/7] MdeModulePkg: Dxe: add RISCV64 to mMachineTypeInfo Andrei Warkentin
2023-03-06 21:26 ` [edk2 6/7] [PATCH v2] UefiCpuPkg: CpuTimerDxeRiscV64: fix tick duration accounting Andrei Warkentin
2023-03-06 21:26 ` [edk2 7/7] [PATCH v3] UefiCpuPkg: BaseRiscV64CpuExceptionHandlerLib: clean up exception handling Andrei Warkentin
2023-03-08 18:37 ` [edk2-devel] [edk2 0/7] v3 Assorted fixes to core RISC-V and RiscVVirt Sunil V L

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