From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web10.1898.1678137984252750213 for ; Mon, 06 Mar 2023 13:26:28 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=dZspeoCT; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: andrei.warkentin@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678137988; x=1709673988; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O3Jkp0nC3L2usB3zsXYl/wUXufNxI7O19fhv3PebexU=; b=dZspeoCTgnYw6vWYNOYffq/TRfhgSMpgVy+ZVqIf+T8SNG1sn7IzE1Dn rikRxuQi6Edyt5lWMA+kaOakzi/40173L3XNHqSW/j/5XWwosYJywfijk TV/yHkMrudQm6T55XIHuCYCdCRKwoZ+s03qeo9eD3Etgf1Y2dMtvoElct SWy+hE6zRHvseen5KOwrAcswrWGLs+VCvIHS7uU7F1fm55+fwLYelIB68 PqyPgA7oEsNgKxJ7mGol5XTmhu1CH3kPQRdCKCA5mtMEFpaHxW+aB9n3s abARQYPLrnlIJfCX59ePPXjuMLHA4nNVY7YbtH4Yc5quxWPkAEazGAEBS Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="315335559" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="315335559" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 13:26:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="819444260" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="819444260" Received: from awarkent-mobl1.amr.corp.intel.com ([10.212.90.17]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 13:26:27 -0800 From: "Andrei Warkentin" To: devel@edk2.groups.io Cc: Andrei Warkentin , Daniel Schaefer , Michael D Kinney , Liming Gao , Zhiguang Liu , Sunil V L Subject: [edk2 3/7] MdePkg: BaseLib: don't log in RISCV InternalSwitchStack Date: Mon, 6 Mar 2023 15:26:11 -0600 Message-Id: <20230306212615.7400-4-andrei.warkentin@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306212615.7400-1-andrei.warkentin@intel.com> References: <20230306212615.7400-1-andrei.warkentin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit InternalSwitchStack may be called with a TPL high enough for a DebugLib implementation to assert. Other arch implementations don't log either. Cc: Daniel Schaefer Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Reviewed-by: Sunil V L Signed-off-by: Andrei Warkentin --- MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c index cf646e498aba..b78424c16383 100644 --- a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c +++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c @@ -44,14 +44,6 @@ InternalSwitchStack ( { BASE_LIBRARY_JUMP_BUFFER JumpBuffer; - DEBUG (( - DEBUG_INFO, - "RISC-V InternalSwitchStack Entry:%x Context1:%x Context2:%x NewStack%x\n", \ - EntryPoint, - Context1, - Context2, - NewStack - )); JumpBuffer.RA = (UINTN)EntryPoint; JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *); JumpBuffer.S0 = (UINT64)(UINTN)Context1; -- 2.25.1